84021 Data Sheet 260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
84021 Rev E 9/23/15 4 ©2015 Integrated Device Technology, Inc
Table 2. Pin Characteristics
Function Tables
Table 3A. Parallel and Serial Mode Function Table
NOTE: L = LOW
H = HIGH
X = Don’t care
= Rising edge transition
= Falling edge transition
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
C
PD
Power Dissipation Capacitance
(per output)
V
DDO
= 3.465V 15 pF
V
DDO
= 2.625V 15 pF
V
DDO
= 1.89V 20 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
R
OUT
Output Impedance
V
DDO
= 3.3V ± 5% 7
V
DDO
= 2.5V ± 5% 7
V
DDO
= 1.8V ± 5% 10
Inputs
ConditionsMR nP_LOAD M N S_LOAD S_CLOCK S_DATA
H X X X X X X Reset. Forces outputs LOW.
L L Data Data X X X
Data on M and N inputs passed directly to the M divider and
N output divider. TEST output forced LOW.
L Data Data L X X
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
LHXXL Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
LHXX LData
Contents of the shift register are passed to the M divider and
N output divider.
LHXX L Data M divider and N output divider values are latched.
L H X X L X X Parallel or serial input do not affect shift registers.
LHXXH Data S_DATA passed directly to M divider as it is clocked.
