MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
10 ______________________________________________________________________________________
To start a conversion, pull
CS
low. At
CS’s
falling edge,
the T/H enters its hold mode and a conversion is initiat-
ed. Data can then be shifted out serially with the exter-
nal clock.
Using
SSHHDDNN
to Reduce Supply Current
Power consumption can be reduced significantly by
shutting down the MAX1084/MAX1085 between conver-
sions. Figure 6 shows a plot of average supply current
vs. conversion rate. The wake-up time, t
WAKE
, is the
time from SHDN deasserted to the time when a conver-
sion may be initiated (Figure 5).This time depends on
the time in shutdown (Figure 7) because the external
4.7µF reference bypass capacitor loses charge slowly
during shutdown and can be as long as 1.4ms.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the
CS
and SCLK digital inputs. The timing
diagrams of Figures 8 and 9 outline serial-interface
operation.
A
CS
falling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of conversion
is determined.
SCLK begins shifting out the data after the rising edge
of the third SCLK pulse. DOUT transitions 20ns after
each SCLK rising edge. The third rising clock edge
produces the MSB of the conversion at DOUT, followed
by the remaining bits. Since there are 12 data bits and
3 leading zeros, at least 15 rising clock edges are
needed to shift out these bits. Extra clock pulses occur-
ring after the conversion result has been clocked out,
and prior to a rising edge of
CS
, produce trailing zeros
at DOUT and have no effect on converter operation.
Pull
CS
high after reading the conversion’s LSB. For
maximum throughput,
CS
can be pulled low again to ini-
tiate the next conversion immediately after the specified
minimum time (t
CS
).
Output Coding and Transfer Function
The data output from the MAX1084/MAX1085 is binary.
Figure 10 depicts the nominal transfer function. Code
transitions occur halfway between successive-integer LSB
values; V
REF
= 2.5V, and 1LSB = 2.44mV or 2.5V/1024.
Applications Information
Connection to Standard Interfaces
The MAX1084/MAX1085 serial interface is fully compat-
ible with SPI, QSPI, and MICROWIRE (Figure 11).
If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the ser-
ial clock. Choose a clock frequency up to 6.4MHz
(MAX1084) or 4.8MHz (MAX1085).
1) Use a general-purpose I/O line on the CPU to pull
CS
low. Keep SCLK low.
2) Activate SCLK for a minimum of 13 clock cycles. The
first two clocks produce zeros at DOUT. DOUT output
data transitions 20ns after SCLK rising edge and is
available in MSB-first format. Observe the SCLK-to-
DOUT valid timing characteristic. Data can be clocked
into the µP on SCLK’s falling or rising edge.
