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MAX1084BCSA+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 7
2.490
2.496
2.494
2.492
2.498
2.500
2.502
2.504
2.506
2.508
2.510
2.5 3.53.0 4.0 4.5 5.0 5.5
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1084/5 toc07
SUPPLY VOLTAGE (V)
V
REF
(V)
2.490
2.496
2.494
2.492
2.500
2.498
2.508
2.506
2.504
2.502
2.510
-40-200 20406080100
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1084/5 toc08
TEMPERATURE (°C)
V
REF
(V)
1.50
2.00
1.75
2.50
2.25
2.75
3.00
2.5 3.5 4.03.0 4.5 5.0 5.5
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1084/5 toc09
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
CONVERTING,
SCLK = 6.4MHz
CONVERTING,
SCLK = 4.8MHz
STATIC
CODE = 1111 1111 1111
R
L
= ∞
C
L
= 10pF
1.5
1.8
2.4
2.1
2.7
3.0
-40 0-20 20406080100
SUPPLY CURRENT vs. TEMPERATURE
MAX1084/5 toc10
TEMPERATURE (
°
C)
SUPPLY CURRENT (mA)
V
DD
= 5V, CONVERTING
V
DD
= 3V, CONVERTING
V
DD
= 5V, STATIC
V
DD
= 3V, STATIC
Typical Operating Characteristics (continued)
(MAX1084: V
DD
= +5.0V, f
SCLK
= 6.4MHz; MAX1085: V
DD
= +3.0V, f
SCLK
= 4.8MHz; C
LOAD
= 20pF, 4.7µF capacitor at REF,
T
A
= +25°C, unless otherwise noted.)
Pin Description
Serial-Clock Input. SCLK drives the conversion process and clocks data out at rates up to 6.4MHz
(MAX1084) or 4.8MHz (MAX1085).
PIN
Positive Supply VoltageV
DD
1
FUNCTIONNAME
Sampling Analog Input, 0 to V
REF
RangeAIN2
Analog and Digital GroundGND5
Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high
impedance.
CS
7
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output. Bypass with a
4.7µF capacitor.
REF4
Active-Low Shutdown Input. Pulling SHDN low shuts down the device and reduces the supply current
to 2µA (typ).
SHDN
3
SCLK8
Serial-Data Output. DOUT changes state at SCLK’s rising edge. High impedance when CS is high.
DOUT6
MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
8 _______________________________________________________________________________________
_______________Detailed Description
Converter Operation
The MAX1084/MAX1085 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 10-bit output.
Figure 3 shows the MAX1084/MAX1085 in their simplest
configuration. The internal reference is trimmed to 2.5V.
The serial interface requires only three digital lines
(SCLK,
CS,
and DOUT) and provides an easy interface to
microprocessors (µPs).
The MAX1084/MAX1085 have two modes: normal and
shutdown. Pulling
SHDN
low shuts the device down and
reduces supply current to 2µA (typ); pulling
SHDN
high
puts the device into operational mode. Pulling CS low ini-
tiates a conversion that is driven by SCLK. The conver-
sion result is available at DOUT in unipolar serial format.
The serial data stream consists of three zeros, followed
by the data bits (MSB first). All transitions on DOUT
occur 20ns after the rising edge of SCLK. Figures 8 and
9 show the interface timing information.
Analog Input
Figure 4 shows the sampling architecture of the ADC’s
comparator. The full-scale input voltage is set by the
internal reference (V
REF
= +2.5V).
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor C
HOLD
. Bringing
CS
low ends the acquisition
interval. At this instant, the T/H switches the input side
of C
HOLD
to GND. The retained charge on C
HOLD
repre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 10-
bit resolution. This action is equivalent to transferring a
charge from C
HOLD
to the binary-weighted capacitive
DOUT DOUT
6kΩ
DGND
C
LOAD
= 20pF C
LOAD
= 20pF
6kΩ
DGND
V
DD
b) HIGH-Z TO V
OL
AND V
OH
TO V
OL
a) HIGH-Z TO V
OH
AND V
OL
TO V
OH
DOUT DOUT
6kΩ
DGND
C
LOAD
= 20pF C
LOAD
= 20pF
6kΩ
DGND
V
DD
b) V
OL
TO HIGH-Za) V
OH
TO HIGH-Z
Figure 1. Load Circuits for DOUT Enable Time
Figure 2. Load Circuits for DOUT Disable Time
MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 9
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of C
HOLD
switches back to AIN, and C
HOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t
ACQ
, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. Acquisition time is calculated by:
t
ACQ
= 7(R
S
+ R
IN
)
✕
12pF
where R
IN
= 800Ω, R
S
= the input signal’s source
impedance, and t
ACQ
is never less than 468ns
(MAX1284) or 625ns (MAX1085). Source impedance
below 4kΩ does not significantly affect the ADC’s AC
performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s input signal
bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 6MHz
(MAX1084) or 3MHz (MAX1085) small-signal band-
width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. To avoid aliasing of unwanted
high-frequency signals into the frequency band of inter-
est, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to V
DD
and GND, allow the input to swing from
(GND - 0.3V) to (V
DD
+ 0.3V) without damage.
If the analog input exceeds 50mV beyond the supplies,
limit the input current to 2mA.
Internal Reference
The MAX1084/MAX1085 have an on-chip voltage refer-
ence trimmed to 2.5V. The internal reference output is
connected to REF and also drives the internal capacitive
DAC. The output can be used as a reference voltage
source for other components and can source up to
800µA. Bypass REF with a 4.7µF capacitor. Larger
capacitors increase wake-up time when exiting shut-
down (see Using
SHDN
to Reduce Supply Current). The
internal reference is disabled in shutdown (SHDN = 0).
Serial Interface
Initialization After Power-Up and
Starting a Conversion
When power is first applied, and if SHDN is not pulled
low, it takes the fully discharged 4.7µF reference
bypass capacitor up to 1.4ms to acquire adequate
charge for specified accuracy. No conversions should
be performed during this time.
C
HOLD
12pF
R
IN
800Ω
HOLD
C
SWITCH
*
6pF
*INCLUDES ALL INPUT PARASITICS
AIN
REF
GND
ZERO
AUTOZERO
RAIL
COMPARATOR
CAPACITIVE DAC
TRACK
SHUTDOWN
INPUT
ANALOG INPUT
0 TO V
REF
+3V to +5V
1
2
3
4
V
DD
AIN
SHDN
REF
8
7
6
5
SCLK
CS
DOUT
GND
SERIAL
INTERFACE
4.7µF
10µF
0.1µF
MAX1084
MAX1085
Figure 3. Typical Operating Circuit
Figure 4. Equivalent Input Circuit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MAX1084BCSA+T

Mfr. #:
Buy MAX1084BCSA+T
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 300/400ksps Sgl-Sply 4Ch Serial 10Bit
Lifecycle:
New from this manufacturer.
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