Data Sheet AD5504
Rev. B | Page 9 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
SYNC
SCLK
SDI
AGND
DGND
SDO
CLR
LDAC
16
15
14
13
12
11
10
9
ALARM
V
DD
R_SEL
V
OUTC
V
OUTD
V
OUTB
V
OUTA
V
LOGIC
TOP VIEW
(Not to Scale)
AD5504
07994-005
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1
CLR
Asynchronous Clear Input. The
CLR
input is falling edge sensitive. When
CLR
is low, all
LDAC
pulses are ignored.
When
CLR
is activated, the input register and the DAC register are set to 0x000 and the outputs to zero scale.
2
SYNC
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When
SYNC
goes
low, it enables the input shift register and data is transferred in on the rising edges of the following clocks. The
selected DAC register is updated on the 16th falling SCLK, unless
SYNC
is taken high before this edge, in which case, the
rising edge of
SYNC
acts as an interrupt, and the write sequence is ignored by the DAC.
3 SCLK Serial Clock Input. Data is clocked into the input shift register on the rising edge of the serial clock input. Data can
be transferred at rates up to 16 MHz.
4 SDI Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the rising edge of the
serial clock input.
5 SDO Serial Data Output. CMOS output. This pin serves as the readback function for all DAC and control registers. Data
is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
6 DGND Digital Ground Pin.
7 AGND Analog Ground Pin.
8
LDAC
Load DAC Input. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new
data. This allows all DAC outputs to update simultaneously. Alternatively, this pin can be tied permanently low.
9 V
OUTD
Buffered Analog Output Voltage from DAC D.
10 V
OUTC
Buffered Analog Output Voltage from DAC C.
11 V
OUTB
Buffered Analog Output Voltage from DAC B.
OUTA
Buffered Analog Output Voltage from DAC A.
13
R_SEL
Range Select Pin. Tying this pin to DGND selects a DAC output range of 0 V to 60 V, alternatively tying
R_SEL
to
V
LOGIC
selects a DAC output range of 0 V to 30 V.
14 V
DD
Positive Analog Power Supply. 10 V to 62 V for the specified performance. This pin should be decoupled with 0.1 µF
ceramic capacitors and 10 µF capacitors.
15
ALARM
Active Low CMOS Output Pin. This pin flags an alarm if the temperature on the die exceeds 110°C.
LOGIC
Logic Power Supply; 2.3 V to 5.5 V. Decouple this pin with 0.1µF ceramic capacitors and 10 µF capacitors.
