Data Sheet AD5504
Rev. B | Page 3 of 20
The serial interface offers the user the capability of both writing
to, and reading from, most of the internal registers. To reduce
power consumption at power up, only the digital section of the
AD5504 is powered up initially. This gives the user the ability to
program the DAC registers to the required value while typically
only consuming 30 μA of supply current. The AD5504 incor-
porates power-on reset circuitry that ensures the DAC registers
power up in a known condition and remain there until a valid
write to the device has taken place. The analog section is
powered up by issuing a power-up command via the SPI
interface. The AD5504 provides software-selectable output
loads while in the power-down mode.
The AD5504 has an on-chip temperature sensor. When the
temperature on the die exceeds 110°C, the
ALARM
pin (an
active low CMOS output pin) flags an alarm and the AD5504
enters a temperature power-down mode disconnecting the
output amplifier thus removing the short-circuit condition. The
AD5504 remains in power-down mode until a software power-up
command is executed.
The AD5504 is available in a compact 16-lead TSSOP. The AD5504
is guaranteed to operate over the extended temperature range of
−40°C to +105°C.
Table 1. Related Device
Part No. Description
AD5501 High Voltage, 12-Bit Voltage Output DAC
AD5504 Data Sheet
Rev. B | Page 4 of 20
SPECIFICATIONS
V
DD
= 10 V to 62 V; V
LOGIC
= 2.3 V to 5.5 V; R
L
= 60 kΩ; C
L
= 200 pF; −40°C < T
A
< +105°C, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ
1
Max Unit Test Conditions/Comments
ACCURACY
2
Resolution 12 Bits
Differential Nonlinearity DNL −1 1 LSB
Integral Nonlinearity INL
60 V Mode −2 +2 LSB V
DD
= 62 V
30 V Mode −3 +3 LSB V
DD
= 62 V
V
OUTX
Temperature Coefficient
3, 4, 5
50
ppm/°C
DAC code = half scale
Zero-Scale Error V
ZSE
100 mV DAC code = 0
Zero-Scale Error Drift
4
60 µV/°C 60 V mode
Offset Error
6
V
OE
−80 +120 mV
Offset Error Drift
4
60 µV/°C 60 V mode
Full-Scale Error V
FSE
−325 +275 mV
Full-Scale Error Drift
4
1 mV/°C 40°C to +25°C; 60 V mode
350 µV/°C +25°C to +105°C; 60 V mode
Gain Error −0.6 +0.6 % of FSR
Gain Temperature Coefficient
4
10 ppm of FSR/°C 60 V mode
DC Crosstalk
4
R
L
= 60 kΩ to AGND or V
DD
Due to Single Channel Full-Scale
Output Change
3 mV 60 V mode
Due to Powering Down (Per Channel) 4 mV 60 V mode
OUTPUT CHARACTERISTICS
Output Voltage Range
7
AGND + 0.5 V
DD
0.5 V
Short-Circuit Current
4, 8
2 mA On any single channel
Capacitive Load Stability
4
1 V to 4 V step
R
L
= 60 kΩ to 1 nF
Load Current
4
−1 +1 mA On any single channel
DC Output Impedance
4
3
DC Output Leakage
4
10 µA
DIGITAL INPUTS
Input Logic High V
IH
2.0 V V
LOGIC
= 4.5 V to 5.5 V
1.8 V V
LOGIC
= 2.3 V to 3.6 V
Input Logic Low V
IL
0.8 V V
LOGIC
= 2.3 V to 5.5 V
Input Current I
IL
±1 µA
Input Capacitance
4
I
IC
5 pF
DIGITAL OUTPUTS
Output High Voltage V
OH
V
LOGIC
0.4 V V I
SOURCE
= 200 µA
Output Low Voltage V
OL
DGND + 0.4 V V I
SINK
= 200 µA
Three-State Leakage Current
SDI, SDO, SCLK,
LDAC
,
CLR
,
R_SEL
−1 +1 µA
ALARM
−10 +10 µA
Output Capacitance
4
5 pF
Data Sheet AD5504
Rev. B | Page 5 of 20
Parameter Symbol Min Typ
1
Max Unit Test Conditions/Comments
POWER SUPPLIES
V
DD
10 62 V
V
LOGIC
2.3 5.5 V
Quiescent Supply Current (I
QUIESCENT
) 2 3 mA Static conditions; DAC
outputs = midscale
Logic Supply Current (I
LOGIC
) 0.4 2 µA V
IH
= V
LOGIC
; V
IL
= DGND
DC PSRR
4
DAC output = full-scale
60 V Mode 68 dB
30 V Mode 76 dB
POWER-DOWN MODE
Supply Current I
DD_PWD
Software Power-Down Mode 30 50 µA
Junction Temperature
8
T
J
130 °C T
J
= T
A
+ P
TOTAL
× θ
JA
1
Typical specifications represent average readings at 25°C, V
DD
= 62 V and V
LOGIC
= 5 V.
2
Valid in output voltage range of (V
DD
0.5 V) to (AGND + 0.5 V). Outputs are unloaded.
3
Includes linearity, offset, and gain drift.
4
Guaranteed by design and characterization. Not production tested.
5
V
OUTX
refers to V
OUTA
, V
OUTB
, V
OUTC
, or V
OUTD
.
6
DAC code = 32 for 60 V mode; DAC code = 64 for 30 V mode.
7
The DAC architecture gives a fixed linear voltage output range of 0 V to 30 V if
R_SEL
is held high and 0 V to 60 V if
R_SEL
is held low. As the output voltage range is
limited by output amplifier compliance, V
DD
should be set to at least 0.5 V higher than the maximum output voltage to ensure compliance.
8
If the die temperature exceeds 110°C, the AD5504 enters a temperature power-down mode putting the DAC outputs into a high impedance state thereby removing
the short-circuit condition. Overheating caused by long term short-circuit condition(s) is detected by an integrated thermal sensor. After power-down, the AD5504
stays powered down until a software power-up command is executed.
AC CHARACTERISTICS
V
DD
= 10 V to 62 V; V
LOGIC
= 2.3 V to 5.5 V; R
L
= 60 kΩ; C
L
= 200 pF; −40°C < T
A
< +10C, unless otherwise noted.
Table 3.
Parameter
1, 2
Min Typ Max Unit Test Conditions/Comments
3
AC CHARACTERISTICS
Output Voltage Settling Time ¼ to ¾ scale settling to ±1 LSB, R
L
= 60 kΩ
60 V Mode
45
55
µs
30 V Mode 25 35 µs
Slew Rate 0.65 V/µs
Digital-to-Analog Glitch Energy 300 nV-s 1 LSB change around major carry in 60 V mode
Glitch Impulse Peak Amplitude 170 mV 60 V mode
Digital Feedthrough 40 nV-s
Digital Crosstalk 5 nV-s
Analog Crosstalk 600 nV-s
DAC-to-DAC Crosstalk 600 nV-s
Peak-to-Peak Noise 140 μV p-p 0.1 Hz to 10 Hz; DAC code = 0x800
4 mV p-p 0.1 Hz to 10 kHz; DAC code = 0x800
1
Guaranteed by design and characterization; not production tested.
2
See the Terminology section.
3
Temperature range is −40°C to + 105°C, typical at 25°C.

AD5504BRUZ-REEL

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Digital to Analog Converters - DAC 5 Chan1nel 40 V DAC
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