AD5504 Data Sheet
Rev. B | Page 16 of 20
SERIAL INTERFACE
The AD5504 has a serial interface (
SYNC
, SCLK, SDI, and
SDO), which is compatible with SPI interface standards, as well
with as most DSPs. The AD5504 allows writing of data, via the
serial interface, to the input and control registers. The DAC
registers are not directly writeable or readable.
The input shift register is 16 bits wide (see Table 8). The 16-bit
word consists of one read/write (R/
W
) control bit, followed by
three address bits and 12 DAC data bits. Data is loaded MSB first.
WRITE MODE
To write to a register, the R/
W
bit should be 0. The three
address bits in the input register (see Table 9) then determine
the register to update. The address bits (A2 to A0) are used for
either DAC register selection or for writing to the control
register. Data is clocked into the selected register during the
remaining 12 clocks of the same frame. Figure 3 shows a timing
diagram of a typical AD5504 write sequence. The write
sequence begins by bringing the
SYNC
line low. Data on the
SDI line is clocked into the 16-bit shift register on the rising
edge of SCLK. On the 16th falling clock edge, the last data bit is
clocked in and the programmed function is executed (that is, a
change in the selected DAC/DACs input register/registers or a
change in the mode of operation). The AD5504 does not
require a continuous SCLK and dynamic power can be saved by
transmitting clock pulses during a serial write only. At this
stage, the
SYNC
line can be kept low or be brought high. In
either case, it must be brought high for a minimum of 20 ns
before the next write sequence for a falling edge of
SYNC
to
initiate the next write sequence. Operate all interface pins close
to the supply rails to minimize power consumption in the
digital input buffers.
READ MODE
The AD5504 allows data readback via the serial interface from
every register directly accessible to the serial interface, which is
all registers except the DAC registers. To read back a register, it
is first necessary to tell the AD5504 that a readback is required.
This is achieved by setting the R/
W
bit to 1. The three address
bits then determine the register from which data is to be read
back. Data from the selected register is then clocked out of the
SDO pin on the next twelve clocks of the same frame.
The SDO pin is normally three-stated but becomes driven on
the rising edge of the fifth clock pulse. The pin remains driven
until the data from the register has been clocked out or the
SYNC
pin is returned high. Figure 4 shows the timing
requirements during a read operation. Note that due to timing
requirements of t
14
(110 ns), the maximum speed of the SPI
interface during a read operation should not exceed 9 MHz.
WRITING TO THE CONTROL REGISTER
The control register is written when Bits[DB14:DB12] are 1.
The control register sets the power-up state of the DAC outputs.
A write to the control register must be followed by another
write operation. The second write operation can be a write to a
DAC input register or a NOP write. Figure 18 shows some
typical combinations.
Table 8. Input Register Bit Map
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R/
W
A2 A1 A0 Data
Table 9. Input Register Bit Functions
Bit Description
R/
W
Indicates a read from or a write to the addressed register.
A2, A1, A0 These bits determine if the input registers or the control register are to be accessed.
A2 A1 A0 Function/Address
0 0 1 DAC A input register
0 1 0 DAC B input register
0 1 1 DAC C input register
1 0 0 DAC D input register
1 0 1 Write data contents to all four DAC input registers
1 1 0 Reserved
1 1 1 Control register
D11:D0 Data bits
