AD5504 Data Sheet
Rev. B | Page 6 of 20
TIMING CHARACTERISTICS
V
DD
= 30 V, V
LOGIC
= 2.3 V to 5.5 V and −40°C < T
A
< +105°C; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter Limit
1
Unit Test Conditions/Comments
t
1
2
60 ns min SCLK cycle time
t
2
10 ns min SCLK high time
t
3
10 ns min SCLK low time
t
4
25 ns min
SYNC
falling edge to SCLK rising edge setup time
t
5
15 ns min Data setup time
6
t
7
0 ns min SCLK falling edge to
SYNC
rising edge
t
8
20 ns min Minimum
SYNC
high time
t
9
20 ns min
LDAC
pulse width low
t
10
50 ns min SCLK falling edge to
LDAC
rising edge
t
11
15 ns min
CLR
pulse width low
t
12
100 ns typ
CLR
pulse activation time
t
13
20 μs typ
ALARM
clear time
t
14
110 ns min SCLK cycle time in read mode
t
15
3
55 ns max SCLK rising edge to SDO valid
t
16
3
25 ns min SCLK to SDO data hold time
17
4
Power-on reset time (this is not shown in the timing diagrams)
t
18
5
50 μs max Power-on time (this is not shown in the timing diagrams)
t
19
5 μs typ ALARM
clear to output amplifier turn on (this is not shown in the timing
diagrams)
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 16.667 MHz.
3
Under load conditions shown in Figure 2.
4
Time from when the V
DD
/V
LOGIC
supplies are powered-up to when a digital interface command can be executed.
5
Time required from execution of power-on software command to when the DAC outputs have settled to 1 V.
V
OH
(MIN) – V
OL
(MAX)
2
200µA I
OL
200µA I
OH
TO OUTPUT
PIN
C
L
50pF
07994-002
Figure 2. Load Circuit for SDO Timing Diagram
