Recommended Circuit Design Parameters
LSTTL-to- TTL-to-
Parameter Symbol LSTTL LSTTL Units Comments Fig. Note
Input
Logic Low Output V
OL
(A) 0.5 0.4 V Maximum
Voltage – Input Gate
Supply Voltage – Input V
CC1
5.0 5.0 V ± 5%
Input Resistor R
IN
360 180 Ω ± 5% 8a
430 200 8b
Input Current I
F
8 16 mA Nominal
Input Current Range I
F
6.75–10 14.0–20 mA 8a
14.5–20 8b
Output
Logic Low Output V
OL
(B) 0.5 0.5 V Maximum
Voltage – HCPL-2533
Supply Voltage – Input V
CC2
5.0 5.0 V ± 5%
Pull-Up Resistor R
L
20 8.2 kΩ ± 5% 13
Required Current Sink I
OL
0.61 1.0 mA Worst Case V
CC
, 14
for Logic Low (max) R
L
, I
IL
(B)
HCPL-2533 Current CTR 11 9 % Minimum T
A
= 0°C to
Transfer Ratio +70°C
Logic Low Output I
OL
0.74 1.26 mA Worst Case V
CC
, CTR, I
F
8a 15
Current – HCPL-2533
(min)
1.30
T
A
= 0°C to +70
°
C
8b
Data Rate f
D
250 250 Kb/s NRZ, T
A
= 25°C 16
Notes:
12. The inverting circuit has higher power consumption and must use open collector gates on the input.
13. The load resistor R
L
must be large enough to guarantee logic LOW and small enough to guarantee logic HIGH under worst case conditions:
V
CC
(max) – V
OL
V
CC
(min) – V
IH
(B)
I
OL
(2533) – I
IL
(B) I
OH
(2533) – I
IH
(B)
The selection of R
L
is the same for both inverting and non-inverting circuits.
14. The maximum current sink required for logic LOW is:
I
OL
(max) = I
IL
(B) (max) + I
R
(max)
where I
R
is the current through R
L
.
15. The ratio of I
OL
(min) to I
OL
(max) gives the design margin for CTR degradation. See Application Note 1002.
16. The maximum data rate is dened as:
1
t
PHL
+ t
PLH
f
D
= bits/second NRZ
≤ R
L
≤
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Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5953-0458
AV02-0521EN - June 19, 2007
