8
Electrical Specications
Over recommended temperature (T
A
= 0°C to +70°C) unless otherwise specied.
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Logic High I
OH
0.5 nA T
A
= 25°C, 5 5
Output Current I
F1
= I
F2
= 0 mA
V
O1
= V
O2
= V
CC
= 5.5 V
50 µA I
F1
= I
F2
= mA 5
V
O1
= V
O2
= V
CC
= 5.5 V
Logic High I
CCH
0.05 4 µA I
F1
= I
F2
= 0 mA
Supply Current V
O1
= V
O2
= Open,
V
CC
= 5.5 V
Input Reverse V
R
5 V I
F
= 10 µA, T
A
= 25°C 5
Breakdown Voltage
Input Capacitance C
IN
60 pF f = 1 MHz, V
F
= 0 V 5
Input-Output I
I–O
1.0 µA 45% Relative Humidity, 7
Insulation Leakage t = 5s
Current V
I–O
= 3000 Vdc,
T
A
= 25°C
Resistance R
I–O
10
12
Ω V
I–O
= 500 Vdc 7
(Input–Output)
Capacitance C
I–O
0.6 pF f = 1 MHz 7
(Input–Output)
Input–Input I
I–I
0.005 µA 45% Relative Humidity, 8
Insulation Leakage t = 5s
Current V
I–I
= 500 Vdc
Resistance R
I–I
10
11
Ω V
I–I
= 500 Vdc 8
(Input–Input)
Capacitance C
I–I
0.25 pF f = 1 MHz 8
(Input–Input)
*All typicals at 25°C.
Notes:
5. Each channel.
6. Current Transfer Ratio is dened as the ratio of output collector current, I
O
, to the forward LED input current, I
F
, times 100%.
7. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
8. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
9. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dV
CM
/dt on the leading edge of the common mode
pulse V
CM
, to assure that the output will remain in a Logic High state (i.e., V
O
> 2.0 V). Common mode transient immunity in Logic Low level is
the maximum tolerable (negative) dV
CM
/dt on the trailing edge of the common mode pulse signal, V
CM
, to assure that the output will remain
in a Logic Low state (i.e., V
O
< 0.8 V).
10. The 7.5 k load represents 1 LSTTL unit load of 0.36 mA and a 20 kΩ pull-up resistor.
11. The 4.7 k load represents 1 LSTTL unit load of 0.36 mA and an 8.2 kΩ pull-up resistor.
