OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

RT8121GQW

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
RT8121
10
DS8121-02 May 2011www.richtek.com
OUT
SS
SS
TD1 is the delay time from power on reset state to the beginning of V rising.
0.7V C
TD1 = 1600μs +
16μA
VID C
TD2 =
16μA
TD3 is the power good delay time.
×
×
down to the voltage specified by VID code. After V
OUT
ramps to V
EAP
= V
DAC
− V
ADJ
, the RT8121 stays in this
state (TD3) and then asserts PGOOD = high. The ramping
slew rate of TD2 is controlled by the external capacitor
connected to SS pin. The voltage of the SS pin will always
be V
EAP
+ 0.7V, where the mentioned 0.7V is the typical
turn-on threshold of an internal power switch. Before
PGOOD = high, the slew rate of V
EAP
is limited to
16μA/C
SS
. When PGOOD = high, the slew rate of V
EAP
is
limited to 160mA/C
SS
. The soft start waveform is shown
in Figure 4.
Figure 4. Soft-Start Waveform
SS
DAC
PGOOD
EN
TD1
TD2
TD3
Soft-Start
Circuit
V
DAC
I
SS
EAP
(Error AMP Positive Input)
Soft-Start Current (I
SS
)
is Limited and Variant
R2
R1
R3
C2
C1C3
V
OUT
FB COMP
ADJSS
C
SS
R
ADJ
+
-
EA
Figure 3. Circuit for Soft-Start and Dynamic VID
RT8121
11
DS8121-02 May 2011 www.richtek.com
Output Voltage Differential Sensing
The RT8121 uses a high-gain low-offset error amplifier for
differential sensing. The CPU voltage is sensed between
the FB and FBRTN pins. A resistor (R
FB
) connects FB pin
with the positive remote sense pin of the CPU (V
CCP
),
while the FBRTN pin connects directly to the negative
remote sense pin of the CPU (V
CCN
). The error amplifier
compares V
EAP
= ( V
DAC
− V
ADJ
) with the V
FB
to regulate
the output voltage.
No-Load Offset
In Figure 5, I
OFSN
and I
OFSP
are used to generate no-load
offset. Either I
OFSN
or I
OFSP
is active during normal
operation. Connect a resistor from OFS pin to GND to
activate I
OFSN
. I
OFSN
flows through R
FB
from the FB pin to
V
CCP
. In this case, a negative no-load offset voltage (V
OFSN
)
is generated.
×
×
FB
OFSN OFSN FB
OFS
0.8 R
V = I R =
R
Connect a resistor from OFS pin to VCC5 to activate I
OFSP
.
I
OFSP
flows through R
FB
from V
CCP
to FB pin. In this case,
a positive no-load offset voltage (V
OFSP
) is generated.
×
×
FB
OFSP OFSP FB
OFS
6.4 R
V = I R =
R
Figure 5. Circuit for V
OUT
Differential Sensing and No-
Load Offset
Load Transient Quick Response
In steady state, the voltage of V
FB
is controlled to be very
close to V
EAP
. While a load step transient from light load
to heavy load could cause V
FB
to be lower than V
EAP
by
several tens of mV. In conventional buck converter design
(without non-linear control) for CPU VR application, due
to limited control bandwidth, it is hard for the VR to prevent
V
OUT
undershoot during quick load transient from light load
to heavy load. Hence, the RT8121 builds in a state-of-
the-art quick response function which detects load
transient by comparing V
FB
and V
EAP
. If V
FB
suddenly
drops below “V
EAP
−V
QR
”where V
QR
is a predetermined
voltage (~40mV), the quick response indicator QR rises
up. When QR = high, the RT8121 turns on all high side
MOSFETs and turns off all low side MOSFETs. The
sensitivity of quick response can be adjusted by varying
the values of C
FB
and R
FB
. Smaller R
FB
and/or larger C
FB
will make QR easier to be triggered. Figure 6 is the circuit
and typical waveforms.
Output Current Sensing
The RT8121 provides a low input offset Current Sense
Amplifier (CSA) to monitor the output current. The output
current of CSA (I
X
) is used for load line control and over
current protection. In this inductor current sensing
topology, R
S
and C
S
must be set according to the equation
below :
×
SS
L
= R C
DCR
Figure 6. Load Transient Quick Response
V
EAP
= V
DAC
- V
ADJ
V
OUT
FB
COMP
R
FB
C
FB
R1
C1
C2
QR Circuit
+
-
EA
I
OUT
V
OUT
QR
C2
+
-
+
V
DAC
-
FBRTN
R
ADJ
ADJ
I
OFSP
R1
C1
C
FB
R
FB
(Positive Remote
Sense Pin of CPU)
V
CC_SNS
V
SS_SNS
(Negative Remote
Sense Pin of CPU)
FB
EAP
COMP
+
-
I
OFSN
RT8121
12
DS8121-02 May 2011www.richtek.com
Load Line
The RT8121 utilizes inductor DCR current sense technique
for load line control function. The sensed inductor current
I
X
is multiplied by 0.5 and sent to ADJ pin. After the current
0.5 x I
X
injects into the ADJ resistors, the voltage of the
ADJ pin is established. The V
ADJ
is then multiplied by 0.1
and subtracted by V
DAC
to generate V
EAP
. Because I
X
is a
PTC (Positive Temperature Coefficient) current, an NTC
(Negative Temperature Coefficient) resistor is needed to
connect ADJ pin to GND. If the NTC resistor is properly
selected to compensate the temperature coefficient of I
X
,
the voltage on ADJ pin will be proportional to I
OUT
without
ADJ x ADJ
ADJ
OUT
A
DJ
OUT OUT ISN
1
V = IR
2
1
V
V
1 DCR 1
10
LL = = = R
II2R10
××
Δ
Δ
×××
ΔΔ
Basically, the resistance of R
ADJ
sets the resistance of
the load line. The temperature coefficient of the R
ADJ
compensates the temperature effect of the load line.
Over Current Protection (OCP)
In Figure 8, V
OCSET
is equal to VCC5 x R2/(R1 + R2). For
the RT8121, V
ADJ
is proportional to I
OUT
and is thermally
compensated. Once V
ADJ
is larger than V
OCSET
, OCP is
triggered and latched. The OCP function will not be
influenced by enabling or disabling load line since the
voltage on the ADJ pin always contains real time
information of load current. Once OCP is triggered, the
RT8121 will turn off both high side MOSFETs and low
side MOSFETs.
Over Voltage Protection (OVP)
The over voltage protection monitors the output voltage
via the FB pin. Once V
FB
exceeds “V
EAP
+ 150mV”, OVP
is triggered and latched. The RT8121 will turn on low side
MOSFET and turn off high side MOSFET to protect CPU.
A 20μs delay is used in OVP detection circuit to prevent
false trigger.
Figure 7. Circuit for Current Sensing
×
L
X
ISN
IDCR
I =
R
Then the output current of CSA will follow the equation
below :
(
××
L OFS-CSA ISP S ISN
X
ISN
I DCR - V + 700n R + R - R
I =
R
700nA is a typical value of the CSA input offset current.
V
OFS-CSA
is the input offset voltage of CSA. V
OFS-CSA
of
the RT8121 is smaller than +/- 1.5mV. Usually, “V
OFS-CSA
+ 700n x (R
ISP
+ R
S
- R
ISN
)” is negligible except at very
light load and the equation can be simplified as the equation
below :
R
ISN
R
ISP
L
DCR
R
S
C
S
ISN
ISP
CSA: Current
Sense Amplifier
R2
C2
C1
R1
V
IN
LGATE
PHASE
UGATE
BOOT
I
X
700nA
V
OFS_CSA
700nA
+
-
+
-
temperature effect. In the RT8121, the positive input of
error amplifier is “V
DAC
− 0.1 x V
ADJ
” and V
OUT
will follow
“V
DAC
− 0.1 x V
ADJ
”. Thus, the output voltage which
decreases linearly with I
OUT
is obtained. The load line is
defined as :
Figure 8. Over Current Protection
VCC5
ADJ
OCSET
OCP
R1
R2
CMP
+
-
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

RT8121GQW

Mfr. #:
Buy RT8121GQW
Manufacturer:
Description:
IC REG CTRLR VID 1OUT 20WQFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet