RT8121
13
DS8121-02 May 2011 www.richtek.com
1) Modulator Characteristic
The modulator consists of the PWM comparator and power
stage. The PWM comparator compares error amplifier EA
output (COMP) with oscillator (OSC) sawtooth wave to
provide a pulse-width modulated (PWM) gate-driving
signal. The PWM wave is smoothed out by the output
filter, L
OUT
and C
OUT
. The output voltage (V
OUT
) is sensed
and fed to the inverting input of the error amplifier.
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
COMP
(output voltage over the error
amplifier output). This transfer function is dominated by a
DC gain, a double pole, and an ESR zero as shown in
Figure 10.
The DC gain of the modulator is the input voltage (V
IN
)
divided by the peak-to-peak oscillator voltage V
OSC
. The
output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter is expressed as :
LC
OUT OUT
1
f =
2 x L x C
π
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires the output
capacitor to have enough ESR to satisfy stability
requirements. The ESR zero of the output capacitor is
expressed as the following equation :
ESR
OUT
1
f =
2 x C x ESR
π
-
+
+
-
OSC
ΔV
OSC
Z
FB
Z
IN
V
IN
Driver
Driver
REF
PWM
Comparator
COMP
EA
+
-
REF
EA
Z
FB
Z
IN
V
OUT
FB
COMP
C1
C2
C3
R1
R2
R3
ESR
C
OUT
V
OUT
L
Figure 9. Compensation Circuit
Loop Compensation
The RT8121 is a voltage mode controller and requires
external compensation. To compensate a typical voltage
mode buck converter, there are two ordinary compensation
schemes, commonly known as type-II compensator and
type-III compensator. The choice of using type-II or
type-III compensator lies with the platform designers, and
the main concern deals with the position of the capacitor
ESR zero and mid-frequency to high frequency gain boost.
Typically, the ESR zero of output capacitor will tend to
stabilize the effect of output LC double poles. Hence, the
position of the output capacitor ESR zero in frequency
domain may influence the design of voltage loop
compensation. Figure 9 shows a typical control loop using
type-III compensator. Below is the compensator design
procedure.
2) Design the Compensator
A well-designed compensator regulates the output voltage
to the reference voltage V
REF
with fast transient response
and good stability. In order to achieve fast transient
response and accurate output regulation, an adequate
compensator design is necessary. The goal of the
compensation network is to provide adequate phase
margin (usually greater than 45°) and the highest bandwidth
(0dB crossing frequency, f
C
) possible. It is also
recommended to manipulate loop frequency response that
its gain crosses over 0dB at a slope of -20dB/dec.
According to Figure 10, the location of poles and zeros
are :
Over Temperature Protection (OTP)
The over temperature protection function of the RT8121 is
built inside the controller to prevent overheat damage. OTP
occurs when the die temperature of the RT8121 exceeds
150°C, in which the RT8121 then turns off both high side
MOSFETs and low side MOSFETs.
