AD8802/AD8804
REV. 0
–6–
HOURS OF OPERATION AT 150°C
0.04
–0.04
0
–0.02
0.02
0
600200 300 500
V
DD
= +4.5V
V
REF
= +4.5V
SS = 176 PCS
x + 2σ
CHANGE IN FULL-SCALE ERROR – LSB
x
x – 2σ
100
400
Figure 13. Full-Scale Error Accelerated by Burn-In
HOURS OF OPERATION AT 150°C
1.0
–1.0
0
–0.5
0.5
INPUT RESISTANCE DRIFT – kΩ
0
600200 300 400
V
DD
= +4.5V
V
REF
= +4.5V
CODE = 55
H
SS = 176 PCS
x + 2σ
x
x – 2σ
100
500
Figure 14. REF Input Resistance Accelerated by Burn-In
OPERATION
The AD8802/AD8804 provides twelve channels of program-
mable voltage output adjustment capability. Changing the pro-
grammed output voltage of each DAC is accomplished by
clocking in a 12-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is four address bits,
MSB first, followed by 8 data bits, MSB first. Table I provides
the serial register data word format. The AD8802/AD8804 has
the following address assignments for the ADDR decode which
determines the location of the DAC register receiving the serial
register data in Bits B7 through B0:
DAC# = A3
×
8 + A2
×
4 + A1
×
2 + A0 + 1
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it pos-
sible to load all 12 DACs in as little time as 4.6 µs (13
×
12
×
30 ns). The exact timing requirements are shown in Figure 15.
Table I. Serial-Data Word Format
ADDR DATA
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
The AD8802 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power-up. The
AD8804 has both a V
REFH
and a V
REFL
pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown
SHDN which places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply
and V
REF
inputs. In shutdown mode the DACX register settings
are maintained. When returning to operational mode from
power shutdown the DAC outputs return to their previous volt-
age settings.
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
DAC REGISTER LOAD
1
0
1
0
1
0
+5V
0V
SDI
CLK
CS
V
OUT
Figure 15a. Timing Diagram
A
X
OR D
X
A
X
OR D
X
1
0
1
0
1
0
+5V
0V
SDI
(DATA IN)
CLK
CS
V
OUT
±1/2 LSB
±1/2 LSB ERROR BAND
t
CSH
t
CL
t
CSS
t
DS
t
DH
t
CS1
DETAIL SERIAL DATA INPUT TIMING (RS = "1")
t
CSW
t
CH
t
S
Figure 15b. Detail Timing Diagram
t
S
t
RS
±1 LSB
±1 LSB ERROR BAND
1
0
+5V
2.5V
RS
V
OUT
RESET TIMING
Figure 15c. Reset Timing Diagram
