AD8802ARUZ-REEL Datasheet AD8804ARUZ, AD8802ARUZ, AD8802ARUZ-REEL | P7-P9

AD8802/AD8804

REV. 0

–7–

PROGRAMMING THE OUTPUT VOLTAGE

The output voltage range is determined by the external refer-

ence connected to V

REFH

and V

REFL

pins. See Figure 16 for a

simplified diagram of the equivalent DAC circuit. In the case of

the AD8802 its V

REFL

is internally connected to GND and

therefore cannot be offset. V

REFH

can be tied to V

and V

REFL

can be tied to GND establishing a basic rail-to-rail voltage out-

put programming range. Other output ranges are established by

the use of different external voltage references. The general

transfer equation which determines the programmed output

voltage is:

VO (Dx) = (Dx)/256 × (V

REFH

– V

REFL

) + V

REFL

Eq. 1

where Dx is the data contained in the 8-bit DACx register.

MSB

P CH

N CH

TO OTHER DACS

GND

REFL

LSB

DAC

REFH

Figure 16. AD8802/AD8804 Equivalent TrimDAC Circuit

For example, when V

REFH

= +5 V and V

REFL

= 0 V, the follow-

ing output voltages will be generated for the following codes:

Output State

D VOx (V

REFH

= +5 V, V

REFL

= 0 V)

255 4.98 V Full Scale

128 2.50 V Half Scale (Midscale Reset Value)

1 0.02 V 1 LSB

0 0.00 V Zero Scale

REFERENCE INPUTS (V

REFH

, V

REFL

)

The reference input pins set the output voltage range of all

twelve DACs. In the case of the AD8802 only the V

REFH

pin is

available to establish a user designed full-scale output voltage.

The external reference voltage can be any value between 0 and

but must not exceed the V

supply voltage. The AD8804

has access to the V

REFL

which establishes the zero-scale output

voltage, any voltage can be applied between 0 V and V

. V

REFL

can be smaller or larger in voltage than V

REFH

since the DAC

design uses fully bidirectional switches as shown in Figure 16.

The input resistance to the DAC has a code dependent variation

which has a nominal worst case measured at 55

, which is ap-

proximately 1.2 kΩ. When V

REFH

is greater than V

REFL

, the

REFL reference must be able to sink current out of the DAC

ladder, while the REFH reference is sourcing current into the

DAC ladder. The DAC design minimizes reference glitch cur-

rent maintaining minimum interference between DAC channels

during code changes.

DAC OUTPUTS (O1–O12)

The twelve DAC outputs present a constant output resistance of

approximately 5 kΩ independent of code setting. The distribu-

tion of R

OUT

from DAC-to-DAC typically matches within ±1%.

However device-to-device matching is process lot dependent

having a ±20% variation. The change in R

OUT

with temperature

has a 500 ppm/°C temperature coefficient. During power shut-

down all twelve outputs are open-circuited.

CLK

SDI

SHDN

AD8802/AD8804

ADDR

DEC

D11

D10

SER

REG

DD0

DAC

REG

DAC

REG

#12

DAC

O10

O11

O12

REFH

GND

(AD8802 ONLY)

REFL

(AD8804 ONLY)

Figure 17. Block Diagram

DIGITAL INTERFACING

The AD8802/AD8804 contains a standard three-wire serial in-

put control interface. The three inputs are clock (CLK),

CS and

serial data input (SDI). The positive-edge sensitive CLK input

requires clean transitions to avoid clocking incorrect data into

the serial input register. Standard logic families work well. If

mechanical switches are used for product evaluation, they

should be debounced by a flip-flop or other suitable means. Fig-

ure 17 block diagram shows more detail of the internal digital

circuitry. When

CS is taken active low, the clock can load data

into the serial register on each positive clock edge, see Table II.

Table II. Input Logic Control Truth Table

CS CLK Register Activity

1 X No effect.

0 P Shifts Serial Register One bit loading the next bit

in from the SDI pin.

P 1 Clock should be high when the

CS returns to the

inactive state.

P = Positive Edge, X = Don’t Care.

The data setup and data hold times in the specification table

determine the data valid time requirements. The last 12 bits of

the data word entered into the serial register are held when

returns high. At the same time

CS goes high it gates the address

decoder which enables one of the twelve positive-edge triggered

DAC registers, see Figure 18 detail.

AD8802/AD8804

REV. 0

–8–

DAC 12

ADDR

DECODE

SERIAL

CLK

SDI

DAC 2

DAC 1

Figure 18. Equivalent Control Logic

The target DAC register is loaded with the last eight bits of the

serial data-word completing one DAC update. Twelve separate

12-bit data words must be clocked in to change all twelve out-

put settings.

All digital inputs are protected with a series input resistor and

parallel Zener ESD structure shown in Figure 19. Applies to

digital input pins

CS, SDI, RS, SHDN, CLK

LOGIC

1kΩ

Figure 19. Equivalent ESD Protection Circuit

Digital inputs can be driven by voltages exceeding the AD8802/

AD8804 V

supply value. This allows 5 V logic to interface

directly to the part when it is operated at 3 V.

APPLICATIONS

Supply Bypassing

Precision analog products, such as the AD8802/AD8804, re-

quire a well filtered power source. Since the AD8802/AD8804

operate from a single +3 V to +5 V supply, it seems convenient

to simply tap into the digital logic power supply. Unfortunately,

the logic supply is often a switch-mode design, which generates

noise in the 20 kHz to 1 MHz range. In addition, fast logic gates

can generate glitches hundred of millivolts in amplitude due to

wiring resistances and inductances.

If possible, the AD8802/AD8804 should be powered directly

from the system power supply. This arrangement, shown in Fig-

ure 20, will isolate the analog section from the logic switching

transients. Even if a separate power supply trace is not available,

however, generous supply bypassing will reduce supply-line in-

duced errors. Local supply bypassing consisting of a 10 µF tan-

talum electrolytic in parallel with a 0.1 µF ceramic capacitor is

recommended (Figure 21).

TTL/CMOS

LOGIC

CIRCUITS

+5V

POWER SUPPLY

10µF

TANT

0.1µF

AD8802/

AD8804

Figure 20. Use Separate Traces to Reduce Power Supply

Noise

AD8802/

AD8804

DGND

10µF

0.1µF

+5V

Figure 21. Recommended Supply Bypassing for the

AD8802/AD8804

Buffering the AD8802/AD8804 Output

In many cases, the nominal 5 kΩ output impedance of the

AD8802/AD8804 is sufficient to drive succeeding circuitry. If a

lower output impedance is required, an external amplifier can

be added. Several examples are shown in Figure 22. One ampli-

fier of an OP291 is used as a simple buffer to reduce the output

resistance of DAC A. The OP291 was chosen primarily for its

rail-to-rail input and output operation, but it also offers opera-

tion to less than 3 V, low offset voltage, and low supply current.

The next two DACs, B and C, are configured in a summing

arrangement where DAC C provides the coarse output voltage

setting and DAC B can be used for fine adjustment. The inser-

tion of R1 in series with DAC B attenuates its contribution to

the voltage sum node at the DAC C output.

REFH

+5V

GND

REFL

DIGITAL INTERFACING

OMITTED FOR CLARITY

100kΩ

OP291

AD8802/

AD8804

SIMPLE BUFFER

0V TO 5V

SUMMER CIRCUIT

WITH FINE TRIM

ADJUSTMENT

Figure 22. Buffering the AD8802/AD8804 Output

Increasing Output Voltage Swing

An external amplifier can also be used to extend the output volt-

age swing beyond the power supply rails of the AD8802/AD8804.

This technique permits an easy digital interface for the DAC,

while expanding the output swing to take advantage of higher

voltage external power supplies. For example, DAC A of Fig-

ure 23 is configured to swing from –5 V to +5 V. The actual

output voltage is given by:

OUT

= 1+









256

×5V

()

–5V

where D is the DAC input value (i.e., 0 to 255). This circuit can

be combined with the “fine/coarse” circuit of Figure 22 if, for

example, a very accurate adjustment around 0 V is desired.

AD8802/AD8804

REV. 0

–9–

REFH

GND

REFL

AD8802/

AD8804

+5V

+12V

–5V

OP191

OP193

100kΩ

–5V TO +4.98V

0V TO +10V

100kΩ

+5V

AD8804

ONLY

Figure 23. Increasing Output Voltage Swing

DAC B of Figure 24 is in a noninverting gain of two configura-

tions, which increases the available output swing to +10 V. The

feedback resistors can be adjusted to provide any scaling of the

output voltage, within the limits of the external op amp power

supplies.

Microcomputer Interfaces

The AD8802/AD8804 serial data input provides an easy inter-

face to a variety of single-chip microcomputers (µCs). Many µCs

have a built-in serial data capability that can be used for com-

municating with the DAC. In cases where no serial port is pro-

vided, or it is being used for some other purpose (such as an

RS-232 communications interface), the AD8802/AD8804 can

easily be addressed in software.

Twelve data bits are required to load a value into the AD8802/

AD8804 (4 bits for the DAC address and 8 bits for the DAC

value). If more than 12 bits are transmitted before the Chip Se-

lect input goes high, the extra (i.e., the most-significant) bits are

ignored. This feature is valuable because most µCs only transmit

data in 8-bit increments. Thus, the µC will send 16 bits to the

DAC instead of 12 bits. The AD8802/AD8804 will only re-

spond to the last 12 bits clocked into the SDI port, however, so

the serial data interface is not affected.

An 8051 µC Interface

A typical interface between the AD8802/AD8804 and an 8051

µC is shown in Figure 24. This interface uses the 8051’s internal

serial port. The serial port is programmed for Mode 0 opera-

tion, which functions as a simple 8-bit shift register. The 8051’s

Port 3.0 pin functions as the serial data output, while Port 3.1

serves as the serial clock.

When data is written to the Serial Buffer Register (SBUF, at

Special Function Register location 99

), the data is automati-

cally converted to serial format and clocked out via Port 3.0 and

Port 3.1. After 8 bits have been transmitted, the Transmit Inter-

rupt flag (SCON.1) is set and the next 8 bits can be transmitted.

The AD8802 and AD8804 require the Chip Select to go low at

the beginning of the serial data transfer. In addition, the SCLK

input must be high when the Chip Select input goes high at the

end of the transfer. The 8051’s serial clock meets this require-

ment, since Port 3.1 both begins and ends the serial data in the

high state.

+5V

P3.0

P3.1

P1.3

P1.2

P1.1

SERIAL DATA

SHIFT REGISTER

RxD

TxD

SHIFT CLOCK

1.11.21.3

PORT 1

SBUF

8051 µC

0.1µF 10µF

O12

GND

AD8802

SDI

SCLK

RESET

SHDN

REFH

Figure 24. Interfacing the 8051

C to an AD8802/AD8804,

Using the Serial Port

Software for the 8051 Interface

A software for the AD8802/AD8804 to 8051 interface is

shown in Listing 1. The routine transters the 8-bit data stored at

data memory location DAC_VALUE to the AD8802/AD8804

DAC addressed by the contents of location DAC_ADDR.

The subroutine begins by setting appropriate bits in the Serial

Control register to configure the serial port for Mode 0 opera-

tion. Next the DAC’s Chip Select input is set low to enable the

AD8802/AD8804. The DAC address is obtained from memory

location DAC_ADDR, adjusted to compensate for the 8051’s

serial data format, and moved to the serial buffer register. At

this point, serial data transmission begins automatically. When

all 8 bits have been sent, the Transmit Interrupt bit is set, and

the subroutine then proceeds to send the DAC value stored at

location DAC_VALUE. Finally the Chip Select input is re-

turned high, causing the appropriate AD8802/AD8804 output

voltage to change, and the subroutine ends.

The 8051 sends data out of its shift register LSB first, while the

AD8802/AD8804 require data MSB first. The subroutine there-

fore includes a BYTESWAP subroutine to reformat the data.

This routine transfers the MSB-first byte at location SHIFT1 to

an LSB-first byte at location SHIFT2. The routine rotates the

MSB of the first byte into the carry with a Rotate Left Carry in-

struction, then rotates the carry into the MSB of the second byte

with a Rotate Right Carry instruction. After 8 loops, SHIFT2

contains the data in the proper format.

The BYTESWAP routine in Listing 1 is convenient because the

DAC data can be calculated in normal LSB form. For example,

producing a ramp voltage on a DAC is simply a matter of re-

peatedly incrementing the DAC_VALUE location and calling

the LD_8802 subroutine.

If the µC’s hardware serial port is being used for other purposes,

the AD8802/AD8804 DAC can be loaded by using the parallel

port. A typical parallel interface is shown in Figure 25. The se-

rial data is transmitted to the DAC via the 8051’s Port 1.6 out-

put, while Port 1.6 acts as the serial clock.

Software for the interface of Figure 25 is contained in Listing 2. The

subroutine will send the value stored at location DAC_VALUE to

the AD8802/AD8804 DAC addressed by location DAC_ADDR.

The program begins by setting the AD8802/AD8804’s Serial

Clock and Chip Select inputs high, then setting Chip Select low

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

AD8802ARUZ-REEL

Mfr. #:

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Manufacturer:

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Description:

Digital to Analog Converters - DAC 12CH 8-Bit w/ Power Shutdown

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