LTC3732CG#TRPBF Datasheet LTC3732CG#PBF, LTC3732CUHF#PBF, LTC3732CG#TRPBF | P10-P12

LTC3732

3732f

OPERATIO

(Refer to Functional Diagram)

FCB pin is below V

–␣ 1.5V but greater than 0.6V, the

controller performs as a Burst Mode switching regulator.

Burst Mode operation sets a minimum output current level

before turning off the top switch and turns off the synchro-

nous MOSFET(s) when the inductor current goes nega-

tive. This combination of requirements will, at low current,

force the I

pin below a voltage threshold that will

temporarily shut off both output MOSFETs until the output

voltage drops slightly. There is a burst comparator having

60mV of hysteresis tied to the I

pin. This hysteresis

results in output signals to the MOSFETs that turn them on

for several cycles, followed by a variable “sleep” interval

depending upon the load current. The resultant output

voltage ripple is held to a very small value by having the

hysteretic comparator after the error amplifier gain block.

B) Stage Shedding Operation

When the FCB pin is tied to the V

pin, Burst Mode

operation is disabled and the forced minimum inductor

current requirement is removed. This provides constant

frequency, discontinuous current operation over the wid-

est possible output current range. At approximately 10%

of maximum designed load current, the second and third

output stages are shut off and the phase 1 controller alone

is active in discontinuous current mode. This “stage

shedding” optimizes efficiency by eliminating the gate

charging losses and switching losses of the other two

output stages. Additional cycles will be skipped when the

output load current drops below 1% of maximum de-

signed load current in order to maintain the output voltage.

This stage shedding operation is not as efficient as Burst

Mode operation at very light loads, but does provide lower

noise, constant frequency operating mode down to very

light load conditions.

C) Continuous Current Operation

Tying the FCB pin to ground will force continuous current

operation. This is the least efficient operating mode, but

may be desirable in certain applications. The output can

source or sink current in this mode. When forcing con-

tinuous operation and sinking current, this current will be

forced back into the main power supply, potentially

boosting the input supply to dangerous voltage levels—

BEWARE!

voltage. When the load current increases, it causes a slight

decrease in the EAIN pin voltage

relative to the 0.6V

reference, which in turn causes the I

voltage to increase

until each inductor’s average current matches one third of

the new load current (assuming all three current sensing

resistors are equal). In Burst Mode operation and stage

shedding mode, after each top MOSFET has turned off, the

bottom MOSFET is turned on until either the inductor

current starts to reverse, as indicated by current compara-

tor I

, or the beginning of the next cycle.

The top MOSFET drivers are biased from floating boot-

strap capacitor C

, which is normally recharged during

each off cycle, through an external Schottky diode. When

decreases to a voltage close to V

OUT

, however, the loop

may enter dropout and attempt to turn on the top MOSFET

continuously. The dropout detector counts the number of

oscillator cycles that the bottom MOSFET remains off and

periodically forces a brief on period to allow C

to re-

charge.

The main control loop is shut down by pulling the RUN/SS

pin low. Releasing RUN/SS allows an internal 1.5µA

current source to charge soft-start capacitor C

. When

reaches 1.5V, the main control loop is enabled and the

internally buffered I

voltage is clamped but allowed to

ramp as the voltage on C

continues to ramp. This “soft-

start” clamping prevents abrupt current from being drawn

from the input power source. When the RUN/SS pin is low,

all functions are kept in a controlled state. The RUN/SS pin

is pulled low when the V

input voltage is below 4V or

when the IC die temperature rises above 150°C.

Low Current Operation

The FCB pin is a multifunction pin: 1) an analog compara-

tor input to provide regulation for a secondary winding by

forcing temporary forced PWM operation and 2) a logic

input to select between three modes of operation.

A) Burst Mode Operation

When the FCB pin voltage is below 0.6V, the controller

performs as a continuous, PWM current mode synchro-

nous switching regulator. The top and bottom MOSFETs

are alternately turned on to maintain the output voltage

independent of direction of inductor current. When the

LTC3732

3732f

OPERATIO

(Refer to Functional Diagram)

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be

synchronized to an external source using the PLLIN pin.

The output of the phase detector at the PLLFLTR pin is also

the DC frequency control input of the oscillator which

operates over a 250kHz to 600kHz range corresponding to

a voltage input from 0V to 2.4V. When locked, the PLL

aligns the turn on of the top MOSFET to the rising edge of

the synchronizing signal. When no frequency information

is supplied to the PLLIN pin, PLLFLTR goes low, forcing

the oscillator to minimum frequency. A DC source can be

applied to the PLLFLTR pin to externally set the desired

operating frequency. An approximate 20µA discharge

current will be present at the pin with no PLLIN signal.

Input capacitance ESR requirements and efficiency losses

are reduced substantially in a multiphase architecture

because the peak current drawn from the input capacitor

is effectively divided by the number of phases used and

power loss is proportional to the RMS current squared. A

3-stage, single output voltage implementation can reduce

input path power loss by 90%.

Differential Amplifier

This amplifier provides true differential output voltage

sensing. Sensing both V

OUT

and V

OUT

–

benefits regula-

tion in high current applications and/or applications hav-

ing electrical interconnection losses. This sensing also

isolates the physical power ground from the physical

signal ground preventing the possibility of troublesome

“ground loops” on the PC layout and prevents voltage

errors caused by board-to-board interconnects, particu-

larly helpful in VRM designs.

Power Good

The PGOOD pin is connected to the drain of an internal

N-channel MOSFET. The MOSFET is turned on once an

internal delay has elapsed and the output voltage has been

away from its nominal value by greater than 10%. If the

output returns to normal prior to the delay timeout, the

timer is reset. There is no delay time for the rising of the

PGOOD output once the output voltage is within the ±10%

“window.”

Short-Circuit Detection

The RUN/SS capacitor is used initially to turn on and limit

the inrush current from the input power source. Once the

controllers have been given time, as determined by the

capacitor on the RUN/SS pin, to charge up the output

capacitors and provide full load current, the RUN/SS

capacitor is then used as a short-circuit timeout circuit. If

the output voltage falls to less than 70% of its nominal

output voltage, the RUN/SS capacitor begins discharging,

assuming that the output is in a severe overcurrent and/or

short-circuit condition. If the condition lasts for a long

enough period, as determined by the size of the RUN/SS

capacitor, the controller will be shut down until the RUN/SS

pin voltage is recycled. This built-in latchoff can be over-

ridden by providing >5µA at a compliance of 4V to the

RUN/SS pin. This additional current shortens the soft-

start period but prevents net discharge of the RUN/SS

capacitor during a severe overcurrent and/or short-circuit

condition. Foldback current limiting is activated when the

output voltage falls below 70% of its nominal level whether

or not the short-circuit latchoff circuit is enabled. Foldback

current limit can be overridden by clamping the EAIN pin

such that the voltage is held above the (70%)(0.6V) or

0.42V level even when the actual output voltage is low.

Input Undervoltage Reset

The RUN/SS capacitor will be reset if the input voltage,

) is allowed to fall below approximately 3.8V. The

capacitor on the RUN/SS pin will be discharged until the

short-circuit arming latch is disarmed. The RUN/SS ca-

pacitor will attempt to cycle through a normal soft-start

ramp up after the V

supply rises above 3.8V. This circuit

prevents power supply latchoff in the event of input power

switching break-before-make situations. The PGOOD pin

is held low during startup until the RUN/SS capacitor rises

above the short-circuit latch-off arming threshold of ap-

proximately 3.8V.

The basic application circuit is shown in Figure 1 on the

first page of this data sheet. External component selection

is driven by the load requirement, and normally begins

with the selection of an inductance value based upon the

desired operating frequency, inductor current and output

LTC3732

3732f

APPLICATIO S I FOR ATIO

WUUU

Operating Frequency

The IC uses a constant frequency, phase-lockable archi-

tecture with the frequency determined by an internal

capacitor. This capacitor is charged by a fixed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to the Phase-Locked

Loop and Frequency Synchronization section for addi-

tional information.

A graph for the voltage applied to the PLLFLTR pin versus

frequency is given in Figure 3. As the operating frequency

is increased the gate charge losses will be higher, reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 680kHz.

MOSFET gate charge and transition losses. In addition to

this basic tradeoff, the effect of inductor value on ripple

current and low current operation must also be consid-

ered. The PolyPhase approach reduces both input and

output ripple currents while optimizing individual output

stages to run at a lower fundamental frequency, enhancing

efficiency.

The inductor value has a direct effect on ripple current. The

inductor ripple current ∆I

per individual section, N,

decreases with higher inductance or frequency and in-

creases with higher V

or V

OUT

∆I

OUT OUT

=−













where f is the individual output stage operating frequency.

In a PolyPhase converter, the net ripple current seen by the

output capacitor is much smaller than the individual

inductor ripple currents due to the ripple cancellation. The

details on how to calculate the net output ripple current

can be found in Application Note 77.

Figure 4 shows the net ripple current seen by the output

capacitors for the different phase configurations. The

output ripple current is plotted for a fixed output voltage as

the duty factor is varied between 10% and 90% on the

x-axis. The output ripple current is normalized against the

inductor ripple current at zero duty factor. The graph can

be used in place of tedious calculations. As shown in

Figure 4, the zero output ripple current is obtained when:

where k N

OUT

==12 1, ,..., –

So the number of phases used can be selected to minimize

the output ripple current and therefore the output ripple

voltage at the given input and output voltages. In applica-

PLLFLTR PIN VOLTAGE (V)

OPERATING FREQUENCY (kHz)

3731 F03

700

600

500

400

300

200

0.5 1 1.5 2 2.5

voltage ripple requirements. Once the inductors and

operating frequency have been chosen, the current sens-

ing resistors can be calculated. Next, the power MOSFETs

and Schottky diodes are selected. Finally, C

and C

OUT

OPERATIO

(Refer to Functional Diagram)

are selected according to the required voltage ripple

requirements. The circuit shown in Figure 1 can be

configured for operation up to a MOSFET supply voltage

of 28V (limited by the external MOSFETs and possibly the

minimum on-time).

Figure 3. Operating Frequency vs V

PLLFLTR

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

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LTC3732CG#TRPBF

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Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators 3-Phase. 5-Bit VID, 600kHz Synch Buck Switching Controller

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