22
LTC3732
3732f
Using L = 0.6µH, a commonly available value results in
34% ripple current. The worst-case output ripple for the
three stages operating in parallel will be less than 11% of
the peak output current.
R
SENSE1,
R
SENSE2
and R
SENSE3
can be calculated by using
a conservative maximum sense current threshold of 65mV
and taking into account half of the ripple current:
R
mV
A
SENSE
=
+
=Ω
65
15 1
34
2
0 0037
%
.
Use a commonly available 0.003Ω sense resistor.
Next verify the minimum on-time is not violated. The
minimum on-time occurs at maximum V
CC
:
t
V
Vf
V
V kHz
ns
ON MIN
OUT
IN MAX
()
=
()
=
()
=
()
.13
20 400
162
The output voltage will be set by the VID code according
to Table 1.
The power dissipation on the topside MOSFET can be
estimated. Using a Fairchild FDS6688 for example, R
DS(ON)
= 7mΩ, C
MILLER
= 15nC/15V = 1000pF. At maximum input
voltage with T(estimated) = 50°C:
P
V
V
CC
A
pF
VV V
kHz W
MAIN
≈
()
+
()
°− °
()
[]
+
()
()()
Ω
()( )
+
()
=
18
20
15 1 0 005 50 25
0 007 20
45
23
2 1000
1
518
1
18
400 2 2
2
2
.
.
.
–. .
.
Ω
The worst-case power dissipation by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem-
perature rise is:
P
VV
V
AW
SYNC
=
−
()()
Ω
()
=
20 1 3
20
15 1 25 0 007 1 84
2
.
.. .
A short circuit to ground will result in a folded back current
of:
I
mV
m
ns V
H
A
SC
≈
+
()
Ω
+
()
µ
=
25
23
1
2
150 20
06
75
.
.
with a typical value of R
DS(ON)
and d = (0.005/°C)(50°C) =
0.25. The resulting power dissipated in the bottom MOSFET
is:
P
SYNC
= (7.5A)
2
(1.25)(0.007Ω) ≈ 0.5W
which is less than one third of the normal, full load
conditions. Incidentally, since the load no longer dissi-
pates any power, total system power is decreased by over
90%. Therefore, the system actually cools significantly
during a shorted condition!
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the layout
diagram of Figure 11. Check the following in the PC layout:
1) Are the signal and power ground paths isolated? Keep the
SGND at one end of a printed circuit path thus preventing
MOSFET currents from traveling under the IC. The IC signal
ground pin should be used to hook up all control circuitry
on one side of the IC, routing the copper through SGND,
under the IC covering the “shadow” of the package, connect-
ing to the PGND pin and then continuing on to the (–) plates
of C
IN
and
C
OUT
. The V
CC
decoupling capacitor should be
placed immediately adjacent to the IC between the V
CC
pin
and PGND. A 1µF ceramic capacitor of the X7R or X5R type
is small enough to fit very close to the IC to minimize the ill
effects of the large current pulses drawn to drive the bottom
MOSFETs. An additional 5µF to 10uF of ceramic, tantalum
or other very low ESR capacitance is recommended in or-
der to keep the internal IC supply quiet. The power ground
returns to the sources of the bottom N-channel MOSFETs,
anodes of the Schottky diodes and (–) plates of C
IN
, which
should have as short lead lengths as possible.
2) Does the IC IN
+
pin connect to the (+) plates of C
OUT
?
A 30pF to 300pF feedforward capacitor between the
DIFFOUT and EAIN pins should be placed as close as
possible to the IC.
APPLICATIO S I FOR ATIO
WUUU
