Integrated Silicon Solution, Inc. - www.issi.com 13
Rev. A
10/22/09
IS42SM83200D / IS42SM16160D / IS42SM32800D
IS42RM83200D / IS42RM16160D / IS42RM32800D
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is
dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures,
requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to
accommodate the worst case, or highest temperature range, expected. Thus, during ambient temperatures, the
power consumed during refresh was unnecessarily high because the refresh rate was set to accommodate the higher
temperatures. Setting E4 and E3 allows the DRAM to accommodate more specific temperature regions during self
refresh. The default for ISSI 256Mb Mobile SDRAM is TCSR = 85°C to guarantee refresh operation. This mode of
operation has a higher current consumption because the self refresh oscillator is set to refresh the SDRAM cells
more often than needed. By using an external temperature sensor to determine the operating temperature the Mobile
SDRAM can be programmed for lower temperature and refresh rates, effectively reducing current consumption by
a significant amount. There are four temperature settings, which will vary the self refresh current according to the
selected temperature. This selectable refresh rate will save power when the Mobile DRAM is operating at normal
temperatures.
Partial-Array Self Refresh (PASR)
For further power savings during self refresh, the PASR feature allows the controller to select the amount of memory
that will be refreshed during self refresh. The refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks
0 and 1); and one bank (bank 0). In addition partial amounts of bank 0 (half or quarter of the bank) may be selected.
WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in
PASR will be refreshed during self refresh. It’s important to note that data in banks 2 and 3 will be lost when the two-
bank option is used. Data will be lost in banks 1, 2, and 3 when the one-bank option is used.
Driver Strength (DS)
Bits E5 and E6 of the EMR can be used to select the driver strength of the DQ outputs. This value should be set
according to the application’s requirements. The default is Full Driver Strength.
Deep Power Down (DPD)
Deep power down mode is for maximum power savings and is achieved by shutting down power to the entire memory
array of the mobile device. Data will be lost once deep power down mode is executed.
DPD mode is entered by having all banks idle, CS and WE held low, with RAS and CAS HIGH at the rising edge of
the clock, while CKE is LOW. CKE must be held LOW during DPD mode. To exit DPD mode, CKE must be asserted
HIGH. Upon exit from DPD mode, at least 200ms of valid clocks with either NOP or COMMAND INHIBIT commands
are applied to the command bus, followed by a full Mobile SDRAM initialization sequence, is required.
