SCC2698BC1A84,518 Datasheet SCC2698BC1A84,512, SCC2698BE1A84,512, SCC2698BE1A84,518 | P10-P12

Philips Semiconductors Product data sheet

SCC2698B

Enhanced octal universal asynchronous

receiver/transmitter (Octal UART)

2006 Aug 07

Note: The transmitter may also control the “RTSN” pin. When un-

der transmitter control the meaning is completely changed. The

meaning is the transmission has ended. This signal is usually used

to switch (turnaround) a bi–directional driver from transmit to re-

ceive.

If the receiver is disabled, the FIFO characters can be read. Howev-

er, no additional characters can be received until the receiver is

enabled again. If the receiver is reset, the FIFO and all of the re-

ceiver status, and the corresponding output ports and interrupt are

reset. No additional characters can be received until the receiver is

enabled again.

Receiver Time–out Mode

The time–out mode uses the received data stream to control the

counter. Each time a received character is transferred from the shift

is not received before the counter reaches zero count, the counter

ready bit is set, and an interrupt can be generated. This mode can

be used to indicate when data has been left in the RxFIFO for more

than the programmed time limit. Otherwise, if the receiver has been

programmed to interrupt the CPU when the receive FIFO is full, and

the message ends before the FIFO is full, the CPU may not know

there is data left in the FIFO. The CTPU and CTPL value would be

programmed for just over one character time, so that the CPU would

be interrupted as soon as it has stopped receiving continuous data.

This mode can also be used to indicate when the serial line has

been marking for longer than the programmed time limit. In this

case, the CPU has read all of the characters from the FIFO, but the

last character received has started the count. If there is no new

data during the programmed time interval, the counter ready bit will

get set, and an interrupt can be generated.

The time–out mode is enabled by writing the appropriate command

to the command register. Writing an ‘Ax’ to CRA or CRB will invoke

the time–out mode for that channel. Writing a ‘Cx’ to CRA or CRB

will disable the time–out mode. The time–out mode should only be

used by one channel at once, since it uses the C/T. If, however, the

time–out mode is enabled from both receivers, the time–out will

occur only when both receivers have stopped receiving data for the

time–out period. CTPU and CTPL must be loaded with a value

greater than the normal receive character period. The time–out

mode disables the regular START/STOP Counter commands and

puts the ca/T into counter mode under the control of the received

data stream. Each time a received character is transferred from the

shift register to the RxFIFO, the C/T is stopped after 1 C/T clock,

reloaded with the value in CTPU and CTPL and then restarted on

the next C/T clock. If the C/T is allowed to end the count before a

new character has been received, the counter ready bit, ISR[3], will

be set. If IMR[3] is set, this will generate an interrupt. Receiving a

character after the C/T has timed out will clear the counter ready bit,

ISR[3], and the interrupt. Invoking the ‘Set Time–out Mode On’

command, CRx = ‘Ax’, will also clear the counter ready bit and stop

the counter until the next character is received.

This mode is cleared by issuing the “Disable Time–out Mode” com-

mand (C0) in the command register.

Time Out Mode Caution

When operating in the special time out mode, it is possible to gener-

ate what appears to be a “false interrupt” – an interrupt without a

cause. This may result when a time–out interrupt occurs and then,

BEFORE the interrupt is serviced, another character is received,

i.e., the data stream has started again. (The interrupt latency is

longer than the pause in the data stream.) In this case, when a new

character has been receiver, the counter/timer will be restarted by

the receiver, thereby withdrawing its interrupt. If, at this time, the

interrupt service begins for the previously seen interrupt, a read of

the ISR will show the “Counter Ready” bit not set. If nothing else is

interrupting, this read of the ISR will return a x’00 character.

Receiver Reset and Disable

Receiver disable stops the receiver immediately – data being

assembled if the receiver shift register is lost. Data and status in the

FIFO is preserved and may be read. A re-enable of the receiver

after a disable will cause the receiver to begin assembling

characters at the next start bit detected. A receiver reset will discard

the present shift register data, reset the receiver ready bit (RxRDY),

clear the status of the byte at the top of the FIFO and re-align the

FIFO read/write pointers. This has the appearance of “clearing or

flushing” the receiver FIFO. In fact, the FIFO is NEVER cleared!

The data in the FIFO remains valid until overwritten by another

received character. Because of this, erroneous reading or extra

reads of the receiver FIFO will miss-align the FIFO pointers and

result in the reading of previously read data. A receiver reset will

re-align the pointers.

WAKE-UP MODE

In addition to the normal transmitter and receiver operation

described above, the Octal UART incorporates a special mode

which provides automatic wake-up of the receiver through address

frame recognition for multiprocessor communications. This mode is

selected by programming bits MR1[4:3] to ‘11’.

In this mode of operation, a ‘master’ station transmits an address

character followed by data characters for the addressed ‘slave’

station. The slave stations, whose receivers are normally disabled,

examine the received data stream and ‘wake-up’ the CPU [by

setting RxRDY) only upon receipt of an address character. The CPU

compares the received address to its station address and enables

the receiver if it wishes to receive the subsequent data characters.

Upon receipt of another address character, the CPU may disable the

receiver to initiate the process again.

A transmitted character consists of a start bit, the programmed

number of data bits, an address/data (A/D) bit, and the programmed

number of stop bits. The polarity of the transmitted A/D bit is

selected by the CPU by programming bit MR1[2]; MR1[2] = 0

transmits a zero in the A/D bit position which identifies the

corresponding data bits as data; MR1[2] = 1 transmits a one in the

A/D bit position which identifies the corresponding data bits as an

address. The CPU should program the mode register prior to

loading the corresponding data bits in the THR.

While in this mode, the receiver continuously looks at the received

data stream, whether it is enabled or disabled. If disabled, it sets the

RxRDY status bit and loads the character in the RHR FIFO if the

received A/D bit is a one, but discards the received character if the

received A/D bit is a zero. If enabled, all received characters are

then transferred to the CPU via the RHR. In either case, the data

bits are loaded in the data FIFO while the A/D bit is loaded in the

status FIFO position normally used for parity error (SR[5]). Framing

error, overrun error, and break detect operate normally whether or

not the receiver is enabled.

The CTS, RTS, CTS Enable Tx signals

CTS (Clear To Send) is usually meant to be a signal to the transmit-

ter meaning that it may transmit data to the receiver. The CTS input

is on pin MPI0 for the transmitter. The CTS signal is active low;

thus, it is called CTSN. RTS is usually meant to be a signal from the

Philips Semiconductors Product data sheet

SCC2698B

Enhanced octal universal asynchronous

receiver/transmitter (Octal UART)

2006 Aug 06

receiver indicating that the receiver is ready to receive data. It is

also active low and is, thus, called RTSN. RTSN is on pin MPO. A

receiver’s RTS output will usually be connected to the CTS input of

the associated transmitter. Therefore, one could say that RTS and

CTS are different ends of the same wire!

MR2(4) is the bit that allows the transmitter to be controlled by the

CTS pin ( MPI0). When this bit is set to one AND the CTS input is

driven high, the transmitter will stop sending data at the end of the

present character being serialized. It is usually the RTS output of

the receiver that will be connected to the transmitter’s CTS input.

The receiver will set RTS high when the receiver FIFO is full AND

the start bit of the fourth character is sensed. Transmission then

stops with four valid characters in the receiver. When MR2(4) is set

to one, CTSN must be at zero for the transmitter to operate. If

MR2(4) is set to zero, the MPI0 pin will have no effect on the opera-

tion of the transmitter.

MR1(7) is the bit that allows the receiver to control MPO. When

MPO is controlled by the receiver, the meaning of that pin will be

RTS. However, a point of confusion arises in that MPO may also be

controlled by the transmitter. When the transmitter is controlling this

pin, its meaning is not RTS at all. It is, rather, that the transmitter

has finished sending its last data byte. Programming the MPO pin

to be controlled by the receiver and the transmitter at the same time

is allowed, but would usually be incompatible.

RTS can also be controlled by the commands 1000 and 1001 in the

command register. RTS is expressed at the MP0 pin which is still an

output port. Therefore, the state of MP0 should be set low (either by

commands of the CR register or by writing to the Output Port Con-

figuration Register) for the receiver to generate the proper RTS sig-

nal. The logic at the output is basically a NAND of the MP0 bit

RTS flow control is selected via the MR1(7) bit the state of the MP0

the MR registers) will return the MP0 pin to the control of the MP0

Transmitter Disable Note

When the TxEMT bit is set the sequence of instructions: enable

transmitter — load transmit holding register — disable transmitter

will often result in nothing being sent. In the condition of the TxEMT

being set do not issue the disable until the TxRDY bit goes active

again after the character is loaded to the TxFIFO. The data is not

sent if the time between the end of loading the transmit holding reg-

ister and the disable command is less that 3/16 bit time in the 16x

mode. One bit time in the 1x mode.

This is sometimes the condition when the RS485 automatic “turn-

around” is enabled . It will also occur when only one character is to

be sent and it is desired to disable the transmitter immediately after

the character is loaded.

In general, when it is desired to disable the transmitter before the

last character is sent AND the TxEMT bit is set in the status register

be sure the TxRDY bit is active immediately before issuing the

transmitter disable instruction. (TxEMT is always set if the transmit-

ter has underrun or has just been enabled), TxRDY sets at the end

of the “start bit” time. It is during the start bit that the data in the

transmit holding register is transferred to the transmit shift register.

MULTI-PURPOSE INPUT PIN

The inputs to this unlatched 8-bit port for each block can be read by

the CPU, by performing a read operation as shown in Table 1. A

High input results in a logic one, while a Low input results in a logic

zero. When the input port pins are read on the 84-pin LLCC, they

will appear on the data bus in alternating pairs (i.e., DB0 = MP10a,

DB1 = MPI1a, DB2 = MPI0b, DB3 = MPI1b, DB4 = MPP1a, DB5 =

MPP2a, DB6 = MPP1b, DB7 = MPP2b. Although this example is

shown for input port ‘A’, all ports will have a similar order).

The MPI pin can be programmed as an input to one of several Octal

UART circuits. The function of the pin is selected by programming

the appropriate control register. Change-of-state detectors are

provided for MPI0 and MPI1 for each channel in each block. A

High-to-Low or Low-to-High transition of the inputs lasting longer

than 25 to 50µs sets the MPI change-of-state bit in the interrupt

status register. The bit is cleared via a command. The

change-of-state can be programmed to generate an interrupt to the

CPU by setting the corresponding bit in the interrupt mask register.

The input port pulse detection circuitry uses a 38.4KHz sampling

clock, derived from one of the baud rate generator taps. This

produces a sampling period of slightly more than 25µs (assuming a

3.6864MHz oscillator input). The detection circuitry, in order to

guarantee that a true change in level has occurred, requires two

successive samples be observed at the new logic level. As a

consequence, the minimum duration of the signal change is 25µs if

the transition occurs coincident with the first sample pulse. (The

50µs time refers to the condition where the change-of-state is just

missed and the first change of state is not detected until after an

additional 25µs.)

MULTI-PURPOSE I/O PINS

The multi-purpose pins (MPP) can be programmed as inputs or

outputs using OPCR[7]. When programmed as inputs, the functions

of the pins are selected by programming the appropriate control

registers. When programmed as outputs, the two MPP1 pins (per

block) will provide the transmitter ready (TxRDY) status for each

channel and the MPP2 pins will provide the receiver ready or FIFO

full (RxRDY/FFULL) status for each channel.

MULTI-PURPOSE OUTPUT PIN

This pin can be programmed to serve as a request-to-send output,

the counter/timer output, the output for the 1X or 16X transmitter or

receiver clocks, the TxRDY output or the RxRDY/FFULL output (see

OPCR [2:0] and OPCR [6:4] – MPO Output Select).

Philips Semiconductors Product data sheet

SCC2698B

Enhanced octal universal asynchronous

receiver/transmitter (Octal UART)

2006 Aug 07

REGISTERS

The operation of the Octal UART is programmed by writing control

words into the appropriate registers. Operational feedback is

provided via status registers which can be read by the CPU.

Addressing of the registers is described in Table 1.

The bit formats of the Octal UART registers are depicted in Table 2.

These are shown for block A. The bit format for the other blocks is

the same.

MR1 – Mode Register 1

MR1 is accessed when the MR pointer points to MR1. The pointer is

set to MR1 by RESET or by a set pointer command applied via the

CR. After reading or writing MR1, the pointers are set at MR2.

MR1[7] – Receiver Request-to-Send Control

This bit controls the deactivation of the RTSN output (MPO) by the

receiver. This output is manually asserted and negated by

commands applied via the command register. MR1[7] = 1 causes

RTSN to be automatically negated upon receipt of a valid start bit if

the receiver FIFO is full. RTSN is reasserted when an empty FIFO

position is available. This feature can be used to prevent overrun in

the receiver by using the RTSN output signal to control the CTS

input of the transmitting device.

MR1[6] – Receiver Interrupt Select

This bit selects either the receiver ready status (RxRDY) or the FIFO

full status (FFULL) to be used for CPU interrupts.

MR1[5] – Error Mode Select

This bit selects the operating mode of the three FIFOed status bits

(FE, PE, received break). In the character mode, status is provided

on a character-by-character basis; the status applies only to the

character at the top of the FIFO. In the block mode, the status

provided in the SR for these bits is the accumulation (logical-OR) of

the status for all characters coming to the top of the FIFO since the

last reset error command was issued.

MR1[4:3] – Parity Mode Select

If ‘with parity’ or ‘force parity’ is selected, a parity bit is added to the

transmitted character and the receiver performs a parity check on

incoming data. MR1[4:3] = 11 selects the channel to operate in the

special wake-up mode.

MR1[2] – Parity Type Select

This bit selects the parity type (odd or even) if the ‘with parity’ mode

is programmed by MR1[4:3], and the polarity of the forced parity bit

if the ‘force parity’ mode is programmed. It has no effect if the ‘no

parity’ mode is programmed. In the special ‘wake-up’ mode, it

selects the polarity of the transmitted A/D bit.

MR1[1:0] – Bits Per Character Select

This field selects the number of data bits per character to be

transmitted and received. The character length does not include the

start, parity, and stop bits.

MR2 – Mode Register 2

MR2 is accessed when the channel MR pointer points to MR2,

which occurs after any access to MR1. Accesses to MR2 do not

change the pointer.

MR2[7:6] – Mode Select

The Octal UART can operate in one of four modes. MR2[7:6] = 00 is

the normal mode, with the transmitter and receiver operating

independently. MR2[7:6] = 01 places the channel in the automatic

echo mode, which automatically re-transmits the received data. The

following conditions are true while in automatic echo mode:

1. Received data is re-clocked and retransmitted on the TxD output.

2. The receive clock is used for the transmitter.

3. The receiver must be enabled, but the transmitter need not be

enabled.

4. The TxRDY and TxEMT status bits are inactive.

5. The received parity is checked, but is not regenerated for

transmission, i.e., transmitted parity bit is as received.

6. Character framing is checked, but the stop bits are retransmitted as

received.

7. A received break is echoed as received until the next valid start bit

is detected.

8. CPU-to-receiver communication continues normally, but the

CPU-to-transmitter link is disabled.

Two diagnostic modes can also be selected. MR2[7:6] = 10 selects

local loopback mode. In this mode:

1. The transmitter output is internally connected to the receiver

input.

2. The transmit clock is used for the receiver.

3. The TxD output is held high.

4. The RxD input is ignored.

5. The transmitter must be enabled, but the receiver need not be

enabled.

6. CPU to transmitter and receiver communications continue

normally.

The second diagnostic mode is the remote loopback mode, selected

by MR2[7:6] = 11. In this mode:

1. Received data is re-clocked and retransmitted on the TXD

output.

2. The receive clock is used for the transmitter.

3. Received data is not sent to the local CPU, and the error status

conditions are inactive.

4. The received parity is not checked and is not regenerated for

transmission, i.e., the transmitted parity bit is as received.

5. The receiver must be enabled, but the transmitter need not be

enabled.

6. Character framing is not checked, and the stop bits are

retransmitted as received.

7. A received break is echoed as received until the next valid start

bit is detected.

The user must exercise care when switching into and out of the

various modes. The selected mode will be activated immediately

upon mode selection, even if this occurs in the middle of a received

or transmitted character. Likewise, if a mode is deselected, the

device will switch out of the mode immediately. An exception to this

is switching out of autoecho or remote loopback modes; if the

deselection occurs just after the receiver has sampled the stop bit

(indicated in autoecho by assertion of RxRDY), and the transmitter

is enabled, the transmitter will remain in autoecho mode until the

entire stop bit has been retransmitted.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

SCC2698BC1A84,518

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UART Interface IC 5V INDUSTRIAL UART 8 CHANNEL

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