Philips Semiconductors Product data sheet
SCC2698B
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
2006 Aug 07
19
DC ELECTRICAL CHARACTERISTICS
1,
2,
3
T
A
= 0 to +70_, V
CC
= 5.0 V " 10%, –40 to 85_C
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
UNITSYMBOL PARAMETER TEST CONDITIONS
Min Typ Max
UNIT
V
IL
Input low voltage 0.8 V
V
IH
Input high voltage (except X1/CLK) 2.0 V
V
IH
Input high voltage (X1/CLK) 0.8V
CC
V
V
OL
V
OH
Output Low voltage
Output High voltage (except OD outputs)
I
OL
= 2.4mA
I
OH
= –400µA
I
OH
= –100µA
0.8V
CC
0.9V
CC
0.4 V
V
V
I
IL
I
IH
Input current Low, MPI and MPP pins
Input current High, MPI and MPP pins
V
IN
= 0
V
IN
= V
CC
–50
20
µA
µA
I
I
Input leakage current V
IN
= 0 to V
CC
–10 10 µA
I
ILX1
I
IHX1
X1/CLK input Low current
X1/CLK input High current
V
IN
= GND, X2 = open
V
IN
= V
CC
, X2 = open
–100
100
µA
µA
I
OZH
I
OZL
Output off current High, 3-State data bus
Output off current Low, 3-State data bus
V
IN
= V
CC
V
IN
= 0
–10
10
µA
I
ODL
I
ODH
Open-drain output Low current in off state: IRQN
Open-drain output Low current in off state: IRQN
V
IN
= V
CC
V
IN
= 0
–10
10
µA
I
CC
Power supply current
Operating mode
30 mA
I
CC
Power down mode
9
2.0 mA
NOTES:
1. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 20ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of V
IL
and V
IH
, as
appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test condition for interrupt and MPP outputs: C
L
= 50pF, R
L
= 2.7kΩ to V
CC
. Test conditions for rest of outputs: C
L
= 150pF.
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must
be negated for t
RWD
guarantee that any status register changes are valid.
7. Consecutive write operations to the command register require at least three edges of the X1 clock between writes.
8. This value is not tested, but is guaranteed by design.
9. See UART applications note for power down currents less than 5µA.
10.Operation to 0MHz is assured by design. Minimum test frequency is 2MHz.
11. Address is latched on leading edge of read or write cycle.
