Philips Semiconductors Product data sheet
SCC2698B
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
2006 Aug 07
26
Table 5. Baud Rates Extended
Normal BRG BRG Test
CSR[7:4] ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1
0000 50 75 4,800 7,200
0001 110 110 880 880
0010 134.5 38.4K 1,076 38.4K
0011 200 150 19.2K 14.4K
0100 300 300 28.8K 28.8K
0101 600 600 57.6K 57.6K
0110 1,200 1,200 115.2K 115.2K
0111 1,050 2,000 1,050 2,000
1000 2,400 2,400 57.6K 57.6K
1001 4,800 4,800 4,800 4,800
1010 7,200 1,800 57.6K 14.4K
1011 9,600 9,600 9,600 9,600
1100 38.4K 19.2K 38.4K 19.2K
1101 Timer Timer Timer Timer
1110 I/O2 – 16X I/O2 – 16X I/O2 – 16X I/O2 – 16X
1111 I/O2 – 1X I/O2 – 1X I/O2 – 1X I/O2 – 1X
NOTE:
Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. This
change affects all receivers and transmitters on the DUART.
The test mode at address H‘A’ changes all transmitters and receivers to the 1x mode and connects the output ports to some internal nodes.
Receiver Reset in the Normal Mode (Receiver Enabled)
Reset can be accomplished easily by issuing a receiver software or hardware reset followed by a receiver enable. All receiver data,
status and programming will be preserved and available before reset. The reset will NOT affect the programming.
Receiver Reset in the Wake-Up Mode (MR1[4:3] = 11)
Reset can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software or
hardware reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and
available before reset. The reset will NOT affect other programming.
The reason for this is the receiver is partially enabled when the parity bits are at ‘11’. Thus the receiver disable and reset is bypassed by
the partial enabling of the receiver.
SD00097
