X4043S8-2.7T1 Datasheet X4043S8Z-2.7, X4043S8IZ-2.7A, X4043M8Z-2.7A | P10-P12

FN8118.3

December 9, 2015

SERIAL INTERFACE

Serial Interface Conventions

The device supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. Therefore, the devices in this fam-

ily operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 6.

Figure 6. Valid Data Changes on the SDA Bus

Serial Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL

is HIGH. The device continuously monitors the SDA

and SCL lines for the start condition and will not

respond to any command until this condition has been

met. See Figure 7.

Serial Stop Condition

All communications must be terminated by a stop con-

dition, which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the device into the standby power mode after a read

sequence. A stop condition can only be issued after the

transmitting device has released the bus. See Figure 6.

Figure 7. Valid Start and Stop Conditions

Serial Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfer. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. Refer to Figure 8.

The device will respond with an acknowledge after

recognition of a start condition and if the correct device

identifier and select bits are contained in the slave

address byte. If a write operation is selected, the

device will respond with an acknowledge after the

receipt of each subsequent eight bit word. The device

will acknowledge all incoming data and address bytes,

except for the slave address byte when the device

identifier and/or select bits are incorrect.

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the device

will continue to transmit data. The device will terminate

further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition

to return the device to standby mode and place the

device into a known state.

SCL

SDA

Data Stable Data Change Data Stable

SCL

SDA

Start Stop

X4043, X4045

FN8118.3

December 9, 2015

Figure 8. Acknowledge Response From Receiver

X4043/45 ADDRESSING

Slave Address Byte

Following a start condition, the master must output a

slave address byte. This byte consists of several parts:

– a device type identifier that is ‘1010’ to access the

array and ‘1011’ to access the control register.

– two bits of ‘0’.

– one bit that becomes the MSB of the address.

– one bit of the slave command byte is a R/W

bit. The

R/W

bit of the slave address byte defines the opera-

tion to be performed. When the R/W

bit is a one,

then a read operation is selected. A zero selects a

write operation. Refer to Figure 8.

– After loading the entire slave address byte from the

SDA bus, the device compares the input slave byte

data to the proper slave byte. Upon a correct compare,

the device outputs an acknowledge on the SDA line.

Word Address

The word address is either supplied by the master or

obtained from an internal counter. The internal counter

is undefined on a power-up condition.

Slave Address Byte

Figure 9. X4043/45 Addressing

Operational Notes

The device powers-up in the following state:

– The device is in the low power standby state.

– The WEL bit is set to ‘0’. In this state it is not possi-

ble to write to the device.

– SDA pin is the input mode.

– RESET

signal is active for t

PURST

SERIAL WRITE OPERATIONS

Byte Write

For a write operation, the device requires the slave

address byte and a word address byte. This gives the

master access to any one of the words in the array.

After receipt of the word address byte, the device

responds with an acknowledge, and awaits the next

eight bits of data. After receiving the 8 bits of the data

byte, the device again responds with an acknowledge.

The master then terminates the transfer by generating a

stop condition, at which time the device begins the inter-

nal write cycle to the nonvolatile memory. During this

internal write cycle, the device inputs are disabled, so the

device will not respond to any requests from the master.

The SDA output is at high impedance. See Figure 10.

A write to a protected block of memory will suppress

the acknowledge bit.

Data Output

from Transmitter

Data Output

from Receiver

81 9

Start Acknowledge

SCL from

Master

Array

Control Reg.

00A8R/W

A7 A6 A5 A4 A3 A2 A1 A0

Word Address

Slave Byte

X4043, X4045

FN8118.3

December 9, 2015

Figure 10. Byte Write Sequence

Page Write

The device is capable of a page write operation. It is

initiated in the same manner as the byte write opera-

tion; but instead of terminating the write cycle after the

first data byte is transferred, the master can transmit

an unlimited number of 8-bit bytes. After the receipt of

each byte, the device will respond with an acknowl-

edge, and the address is internally incremented by

one. The page address remains constant. When the

counter reaches the end of the page, it “rolls over” and

goes back to ‘0’ on the same page. This means that

the master can write 16 bytes to the page starting at

any location on that page. If the master begins writing

at location 10, and loads 12 bytes, then the first 5

bytes are written to locations 10 through 15, and the

last 7 bytes are written to locations 0 through 6. After-

wards, the address counter would point to location 7 of

the page that was just written. If the master supplies

more than 16 bytes of data, then new data over-writes

the previous data, one byte at a time.

Figure 11. Page Write Operation

Figure 12. Writing 12-bytes to a 16-byte page starting at location 10

The master terminates the data byte loading by issu-

ing a stop condition, which causes the device to begin

the nonvolatile write cycle. As with the byte write opera-

tion, all inputs are disabled until completion of the inter-

nal write cycle. See Figure 11 for the address,

acknowledge, and data transfer sequence.

Stops and Write Modes

Stop conditions (that terminate write operations) must

be sent by the master after sending at least 1 full data

byte, plus the subsequent ACK signal. If a stop is

issued in the middle of a data byte, or before 1 full data

byte plus its associated ACK is sent, then the device

will reset itself without performing the write. The con-

tents of the array will not be effected.

Slave

Address

Byte

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Slave

Address

Byte

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(1)

(1  n 16)

Address

5 Bytes

n-1

7 Bytes

Address

= 6

Address Pointer

Ends Here

Addr = 7

X4043, X4045

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

X4043S8-2.7T1

Mfr. #:

Buy X4043S8-2.7T1

Manufacturer:

Renesas / Intersil

Description:

IC SUPERVISOR CPU 4K EE 8-SOIC

Lifecycle:

New from this manufacturer.

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X4043S8-2.7T1

X4043S8-2.7T1

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