16
FN8118.3
December 9, 2015
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with
respect to V
SS
...................................... -1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave
address byte are incorrect; 200ns after a stop ending a read operation; or t
WC
after a stop ending a write operation.
(2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t
WC
after a stop that initiates a
nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte.
(3) V
IL
min. and V
IH
max. are for reference only and are not tested.
Symbol Parameter
V
CC
= 2.7 to 5.5V
Unit Test ConditionsMin. Max.
I
CC1
(1)
Active supply current read 1.0 mA V
IL
= V
CC
x 0.1, V
IH
= V
CC
x 0.9
f
SCL
= 400kHz
I
CC2
(1)
Active supply current write 3.0 mA
I
SB1
(2)
Standby current AC (WDT off) 1 µA V
IL
= V
CC
x 0.1, V
IH
= V
CC
x 0.9
f
SCL
= 400kHz, SDA = open
V
CC
= 1.22 x V
CC
min
I
SB2
(2)
Standby current DC (WDT off) 1 µA V
SDA
= V
SCL
= V
SB
Others = GND or V
SB
I
SB3
(2)
Standby current DC (WDT on) 20 µA V
SDA
=V
SCL
= V
SB
Others = GND or V
SB
I
LI
Input leakage current 10 µA V
IN
= GND to V
CC
I
LO
Output leakage current 10 µA V
SDA
= GND to V
CC
device is in standby
V
IL
(3)
Input LOW voltage -0.5 V
CC
x 0.3 V
V
IH
(3)
Input nonvolatile V
CC
x 0.7 V
CC
+ 0.5 V
V
HYS
Schmitt trigger input hysteresis
Fixed input level
V
CC
related level
0.2
.05 x V
CC
V
V
V
OL
Output LOW voltage 0.4 V I
OL
= 3.0mA (2.7-5.5V)
I
OL
= 1.8mA (2.0-3.6V)
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C 70°C
Industrial -40°C +85°C
Option Supply Voltage Limits
-2.7 and -2.7A 2.7V to 5.5V
Blank and -4.5A 4.5V to 5.5V
X4043, X4045
17
FN8118.3
December 9, 2015
CAPACITANCE (T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V)
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Notes: (5) Typical values are for T
A
= 25°C and V
CC
= 5.0V
(6) Cb = total capacitance of one bus line in pF.
Symbol Parameter Max. Unit Test Conditions
C
OUT
(4)
Output capacitance (SDA, RESET/RESET) 8 pF V
OUT
= 0V
C
IN
(4)
Input capacitance (SCL, WP) 6 pF V
IN
= 0V
5V
4.6k
RESET
100pF
SDA
1533
100pF
5V
For V
OL
= 0.4V
and I
OL
= 3 mA
Input pulse levels 0.1 V
CC
to 0.9 V
CC
Input rise and fall times 10ns
Input and output timing levels 0.5 V
CC
Output load Standard output load
Symbol Parameter
100kHz 400kHz
UnitMin. Max. Min. Max.
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
IN
Pulse width suppression time at inputs n/a n/a 50 ns
t
AA
SCL LOW to SDA data out valid 0.1 0.9 0.1 0.9 µs
t
BUF
Time the bus free before start of new transmission 4.7 1.3 µs
t
LOW
Clock LOW time 4.7 1.3 µs
t
HIGH
Clock HIGH time 4.0 0.6 µs
t
SU:STA
Start condition setup time 4.7 0.6 µs
t
HD:STA
Start condition hold time 4.0 0.6 µs
t
SU:DAT
Data in setup time 250 100 ns
t
HD:DAT
Data in hold time 5.0 0 µs
t
SU:STO
Stop condition setup time 0.6 0.6 µs
t
DH
Data output hold time 50 50 ns
t
R
SDA and SCL rise time 1000 20 + .1Cb
(6)
300 ns
t
F
SDA and SCL fall time 300 20 + .1Cb
(6)
300 ns
t
SU:WP
WP setup time 0.4 0.6 s
t
HD:WP
WP hold time 0 0 s
Cb Capacitive load for each bus line 400 400 pF
X4043, X4045
18
FN8118.3
December 9, 2015
TIMING DIAGRAMS
Bus Timing
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Notes: (7) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used.
Symbol Parameter Min. Typ.
(7)
Max. Unit
t
WC
(7)
Write cycle time 5 10 ms
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
AA
t
R
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
Clk 1 Clk 9
Slave Address Byte
START
SCL
SDA
t
WC
8
th
Bit of Last Byte ACK
Stop
Condition
Start
Condition
X4043, X4045

X4043S8-2.7T1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC SUPERVISOR CPU 4K EE 8-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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