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X4043S8-2.7T1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
4
FN8118.3
December 9, 2015
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock
protection.
The array is internally organized as x 8. The device
features an 2-wire interface and software protocol
allowing operation on an I
2
C bus.
The device utilizes Intersil’s proprietary Direct Write
™
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
NC
V
SS
V
CC
SDA
SCL
3
2
4
1
6
7
5
8
NC
WP
RESET
8-Pin JEDEC SOIC, MSOP
(PDIP no longer available or supported)
Pin
(SOIC/MSOP/DIP) Name Function
1 NC No internal connections
2 NC No internal connections
3 RESET
/RESET Reset Output. RESET is an active LOW, open drain output which goes active
whenever V
CC
falls below V
TRIP
. It will remain active until V
CC
rises above the
V
TRIP
for t
PURST
. RESET/RESET goes active if the Watchdog Timer is enabled
and SDA remains either HIGH or LOW longer than the selectable Watchdog time
out period. RESET
/RESET goes active on power-uppower-up and remains
active for 250ms after the power supply stabilizes. RESET is an active high open
drain output. An external pull up resistor is required on the RESET
/RESET pin.
4V
SS
Ground
5SDASerial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
6SCLSerial Clock. The Serial Clock input controls the serial bus timing for data input and
output.
7WPWrite Protect. WP HIGH prevents writes to any location in the device (including
the control register). Connect WP pin to V
SS
when it is not used.
8V
CC
Supply Voltage
X4043, X4045
5
FN8118.3
December 9, 2015
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4043/45 activates a
Power-on Reset Circuit that pulls the RESET
/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
When V
CC
exceeds the device V
TRIP
threshold value
for 200ms (nominal) the circuit releases
RESET
/RESET allowing the system to begin operation.
Low Voltage Monitoring
During operation, the X4043/45 monitors the V
CC
level
and asserts RESET
/RESET if supply voltage falls
below a preset minimum V
TRIP
. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET
/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
CC
returns and exceeds
V
TRIP
for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
(RESET/RESET
) signal going active. A minimum
sequence to reset the watchdog timer requires four
microprocessor intructions namely, a Start, Clock Low,
Clock High and Stop. (See Page 18) The state of two
nonvolatile control bits in the status register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
Figure 1. Watchdog Restart
EEPROM Inadvertent Write Protection
When RESET
/RESET goes active as a result of a low
voltage condition (V
CC
< V
TRIP
), any in-progress com-
munications are terminated. While V
CC
< V
TRIP
, no new
communications are allowed and no nonvolatile write
operation can start. Nonvolatile writes in-progress when
RESET
/RESET goes active are allowed to finish.
Additional protection mechanisms are provided with
memory block lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
TRIP
Programming
The X4043/45 is shipped with a standard V
CC
thresh-
old (V
TRIP
) voltage. This value will not change over
normal operating and storage conditions. However, in
applications where the standard V
TRIP
is not exactly
right, or if higher precision is needed in the V
TRIP
value, the X4043/45 threshold may be adjusted. The
procedure is described below, and uses the applica-
tion of a high voltage control signal.
Figure 2. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
values WEL bit set)
SCL
SDA
.6µs
1.3µs
Start StopResetWDT
01234567
SCL
SDA
A0h
01234567
01h
WP
V
P
= 15-18V
01234567
00h
X4043, X4045
6
FN8118.3
December 9, 2015
Setting a V
TRIP
Voltage
There are two procedures used to set the threshold
voltages (V
TRIP
), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present V
TRIP
is 2.9 V and the new
V
TRIP
is 3.2 V, the new voltage can be stored directly
into the V
TRIP
cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the V
TRIP
voltage before setting the new value.
Setting a Higher V
TRIP
Voltage
To set a V
TRIP
threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired V
TRIP
threshold voltage to the V
CC
. Then,
a programming voltage (Vp) must be applied to the
WP pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h,
followed by the Byte Address 01h for V
TRIP
and a 00h
Data Byte in order to program V
TRIP
. The STOP bit
following a valid write operation initiates the program-
ming sequence. WP pin must then be brought LOW to
complete the operation.
To check if the V
TRIP
has been set, first power-down
the device. Slowly ramp up V
CC
and observe when the
output, RESET
(4043) or RESET (4045) switches. The
voltage at which this occurs is the V
TRIP
(actual) (see
Figure 2).
C
ASE A
Now if the desired V
TRIP
is greater than the V
TRIP
(actual), then add the difference between V
TRIP
(desired) - V
TRIP
(actual) to the original V
TRIP
desired.
This is your new V
TRIP
that should be applied to V
CC
and the whole sequence should be repeated again
(see Figure 5).
C
ASE B
Now if the V
TRIP
(actual), is higher than the V
TRIP
(desired), perform the reset sequence as described in
the next section. The new V
TRIP
voltage to be applied to
V
CC
will now be: V
TRIP
(desired) - (V
TRIP
(actual)-V
TRIP
(desired)).
Note: This operation does not corrupt the memory
array.
Setting a Lower V
TRIP
Voltage
In order to set V
TRIP
to a lower voltage than the pres-
ent value, then V
TRIP
must first be “reset” according to
the procedure described below. Once V
TRIP
has been
“reset”, then V
TRIP
can be set to the desired voltage
using the procedure described in “Setting a Higher
V
TRIP
Voltage”.
Resetting the V
TRIP
Voltage
To reset a V
TRIP
voltage, apply the programming volt-
age (Vp) to the WP pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h fol-
lowed by 00h for the Data Byte in order to reset V
TRIP
.
The STOP bit following a valid write operation initiates
the programming sequence. Pin WP must then be
brought LOW to complete the operation.
After being reset, the value of V
TRIP
becomes a nomi-
nal value of 1.7V or lesser.
Note: This operation does not corrupt the memory
array.
X4043, X4045
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

X4043S8-2.7T1

Mfr. #:
Buy X4043S8-2.7T1
Manufacturer:
Renesas / Intersil
Description:
IC SUPERVISOR CPU 4K EE 8-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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