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CYPT1542AV18-250GCMB

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CYRS1542AV18
CYRS1544AV18
72-Mbit QDR
®
II+ SRAM Two-Word
Burst Architecture with RadStop™ Technology
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-60006 Rev. *M Revised January 9, 2015
72-Mbit QDR
®
II+ SRAM Two-Word Burst Architecture with RadStop™ Technology
Radiation Performance
Radiation Data
■ Total Dose =300 Krad
■ Soft error rate (both Heavy Ion and proton)
Heavy ions 1 × 10
-10
upsets/bit-day with an external SECDED
EDAC Controller
■ Neutrons = 2.0 × 10
14
N/cm
2
■ Dose rate = 2.0 × 10
9
rad(Si)/sec
■ Dose rate survivability (rad(Si)/sec) = 1.5 × 10^11 rad(Si)/sec
■ Latch up immunity = 120 MeV.cm
2
/mg (125 °C)
Prototyping Options
■ Non qualified CYPT1542AV18 and CTPT1544AV18 devices
with same functional and timing characteristics in a 165-ball
Ceramic Column Grid Array (CCGA) package
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 250-MHz clock for high bandwidth
■ Two-word burst on all accesses
■ Double data rate (DDR) interfaces on both read and write ports
at 250 MHz (data transferred at 500 MHz)
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR
®
II operates with 2.0 cycle read latency when delay lock
loop (DLL) is enabled
■ Available in × 18 and × 36 configurations
■ Full data coherency, providing most current data
■ Core V
DD
= 1.8 V (±0.1 V); I/O V
DDQ
= 1.4 V to V
DD
■ Available in 165-ball CCGA (21 × 25 × 2.83 mm)
■ HSTL inputs and variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ DLL for accurate data placement
Configurations
CYRS1542AV18 – 4 M × 18
CYRS1544AV18 – 2 M × 36
Functional Description
The CYRS1542AV18 and CYRS1544AV18 are synchronous
pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with
RadStop™ technology. Cypress’s state-of-the-art RadStop
Technology is radiation hardened through proprietary design and
process hardening techniques.
The QDR II+ architecture consists of two separate ports to
access the memory: the read port and the write port. The read
port has dedicated data output bus to support read operations
and the write port has dedicated data input bus to support write
operations. QDR II+ architecture completely eliminates the need
to “turnaround” the data bus that exists with common I/O devices.
Each port is accessed through a common address bus.
Addresses for read are latched on the rising edges of the input
(K) clock whereas addresses for write are latched on the falling
edges of the input (K) clock. Accesses to the QDR II+ read and
write ports are completely independent of each another. To
maximize data throughput, both read and write ports are
equipped with DDR interfaces. Each address location is
associated with two 18-bit words for CYRS1542AV18, or two
36-bit words for CYRS1544AV18 that burst sequentially into or
out of the device. Since data can be transferred on every rising
edge of both input clocks (K and K#), memory bandwidth is
maximized while simplifying system design by eliminating bus
“turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K
input clocks. All data outputs pass through output
registers controlled by the K or K
input clocks as well. Reads and
writes are conducted with on-chip synchronous self-timed
circuitry.
For a complete list of related resources, click here.
Selection Guide
Description 250 MHz Unit
Maximum operating frequency 250 MHz
Maximum operating current
(concurrent R/W)
× 18 1700 mA
× 36 1700
CYRS1542AV18
CYRS1544AV18
Document Number: 001-60006 Rev. *M Page 2 of 34
Logic Block Diagram – CYRS1542AV18
Logic Block Diagram – CYRS1544AV18
2M x 18 Array
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
36
18
BWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
18
A
(20:0)
21
CQ
CQ
DOFF
Q
[17:0]
18
18
Write
Reg
2M x 18 Array
18
QVLD
1M x 36 Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
72
36
BWS
[3:0]
V
REF
Write Add. Decode
Write
Reg
36
A
(19:0)
20
CQ
CQ
DOFF
Q
[35:0]
36
36
Write
Reg
1M x 36 Array
36
QVLD
CYRS1542AV18
CYRS1544AV18
Document Number: 001-60006 Rev. *M Page 3 of 34
Contents
Manufacturing Flow ..........................................................4
Radiation Hardened Design ........................................4
Neutron Soft Error Immunity ...........................................4
Pin Configuration .............................................................5
Pin Definitions ..................................................................6
Functional Overview ........................................................8
Read Operations .........................................................8
Write Operations .........................................................8
Byte Write Operations .................................................8
Concurrent Transactions .............................................8
Depth Expansion .........................................................8
Programmable Impedance ..........................................8
Echo Clocks ................................................................9
Valid Data Indicator (QVLD) ........................................9
DLL ..............................................................................9
Qualification and Screening ........................................9
Application Example ......................................................10
Truth Table ......................................................................11
Write Cycle Descriptions ...............................................11
Write Cycle Descriptions ...............................................12
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................13
Disabling the JTAG Feature ......................................13
Test Access Port .......................................................13
Performing a TAP Reset ...........................................13
TAP Registers ...........................................................13
TAP Instruction Set ...................................................13
TAP Controller State Diagram .......................................15
TAP Controller Block Diagram ......................................16
TAP Electrical Characteristics ......................................16
TAP AC Switching Characteristics ...............................17
TAP Timing and Test Conditions ..................................18
Identification Register Definitions ................................19
Scan Register Sizes .......................................................19
Instruction Codes ...........................................................19
Boundary Scan Order ....................................................20
Power Up Sequence in QDR II+ SRAM .........................21
Power Up Sequence .................................................21
DLL Constraints .........................................................21
Maximum Ratings ...........................................................22
Operating Range .............................................................22
Electrical Characteristics ...............................................22
DC Electrical Characteristics .....................................22
AC Electrical Characteristics .....................................23
Radiation Performance ..................................................23
Capacitance ....................................................................23
Thermal Resistance ........................................................23
AC Test Loads and Waveforms .....................................24
Switching Characteristics ..............................................25
Switching Waveforms ....................................................26
Ordering Information ......................................................27
Ordering Code Definitions .........................................27
Package Diagram ............................................................28
Acronyms ........................................................................29
Document Conventions .................................................29
Units of Measure .......................................................29
Glossary ..........................................................................30
Document History Page .................................................31
Sales, Solutions, and Legal Information ......................34
Worldwide Sales and Design Support ....................... 34
Products ....................................................................34
PSoC® Solutions ......................................................34
Cypress Developer Community .................................34
Technical Support .....................................................34
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CYPT1542AV18-250GCMB

Mfr. #:
Buy CYPT1542AV18-250GCMB
Manufacturer:
Cypress Semiconductor
Description:
SRAM 72Mb 1.8V 250Mhz 4M x 18 QDR II SRAM
Lifecycle:
New from this manufacturer.
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