CYRS1542AV18
CYRS1544AV18
Document Number: 001-60006 Rev. *M Page 11 of 34
Truth Table
CYRS1542AV18 and CYRS1544AV18
[2, 3, 4, 5, 6, 7]
Operation K RPS WPS DQ DQ
Write cycle:
Load address on the rising edge of K;
input write data on K and K
rising edges.
L–H X L D(A) at K(t) D(A + 1) at K(t)
Read cycle:(2.0 cycle Latency)
Load address on the rising edge of K;
wait two cycles; read data on K
and K rising edges.
L–H L X Q(A) at K(t + 2) Q(A + 1) at K
(t + 2)
NOP: No operation L–H H H D = X
Q = High Z
D = X
Q = High Z
Standby: Clock stopped Stopped X X Previous state Previous state
Write Cycle Descriptions
CYRS1542AV18
[2, 8]
BWS
0
BWS
1
K
K
Comments
L L L–H – During the data portion of a write sequence Both bytes (D
[17:0]
) are written into the device.
L L – L–H During the data portion of a write sequence: Both bytes (D
[17:0]
) are written into the device.
L H L–H – During the data portion of a write sequence
Only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
L H – L–H During the data portion of a write sequence
Only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
H L L–H – During the data portion of a write sequence
Only the upper byte (D
[17:9]
) is written into the device, D
[8:0]
remains unaltered.
H L – L–H During the data portion of a write sequence
Only the upper byte (D
[17:9]
) is written into the device, D
[8:0]
remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K
rising edges. Data outputs are delivered on K and K rising edges.
7. It is recommended that K = K
= HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS
0
, BWS
1
,
BWS
2
and BWS
2
can be altered on different portions
of a write cycle, as long as the setup and hold requirements are achieved.
