CYRS1542AV18
CYRS1544AV18
Document Number: 001-60006 Rev. *M Page 25 of 34
Switching Characteristics
Over the Operating Range
Parameters
[29, 30]
Description
250 MHz
Unit
Cypress
Parameter
Consortium
Parameter
Min Max
t
POWER
V
DD
(typical) to the first access
[31]
1–ms
t
CYC
t
KHKH
K clock cycle time 4.0 8.4 ns
t
KH
t
KHKL
Input clock (K/K) HIGH 1.6 – ns
t
KL
t
KLKH
Input clock (K/K) LOW 1.6 – ns
t
KHKH
t
KHKH
K clock rise to K clock rise (rising edge to rising edge) 1.8 – ns
Setup Times
t
SA
t
AVKH
Address setup to K clock rise 0.5 – ns
t
SC
t
IVKH
Control setup to K clock rise
(RPS
, WPS)
0.5 – ns
t
SCDDR
t
IVKH
DDR control setup to clock (K/K) rise (BWS
0
, BWS
1
, BWS
2
, BWS
3
)0.5–ns
t
SD
t
DVKH
D
[X:0]
setup to clock (K/K) rise 0.5 – ns
Hold Times
t
HA
t
KHAX
Address hold after K clock rise 0.5 – ns
t
HC
t
KHIX
Control hold after K clock rise
(RPS
, WPS)
0.5 – ns
t
HCDDR
t
KHIX
DDR control hold after clock (K/K) rise (BWS
0
, BWS
1
, BWS
2
, BWS
3
)0.5 –ns
t
HD
t
KHDX
D
[X:0]
hold after clock (K/K) rise 0.5 – ns
Output Times
t
CO
t
CHQV
K/K clock rise to data valid
–0.85ns
t
DOH
t
CHQX
Data output hold after output K/K clock rise (Active to active)
–0.85 – ns
t
CCQO
t
CHCQV
K/K clock rise to echo clock valid
–0.85ns
t
CQOH
t
CHCQX
Echo clock hold after C/C clock rise
–0.5 – ns
t
CQD
t
CQHQV
Echo clock high to data valid – 0.50 ns
t
CQDOH
t
CQHQX
Echo clock high to data invalid –0.30 – ns
t
CQH
t
CQHCQL
Output clock (CQ/CQ) HIGH
[32]
1.55 – ns
t
CQHCQH
t
CQHCQH
CQ clock rise to CQ clock rise
(rising edge to rising edge)
[32]
1.55 – ns
t
CHZ
t
CHQZ
Clock (K/K) rise to high Z (active to high Z)
[33, 34]
–0.45ns
t
CLZ
t
CHQX1
Clock (K/K) rise to low Z
[33, 34]
–0.45 – ns
t
QVLD
t
CQHQVLD
Echo Clock High to QVLD Valid
[35]
–0.5 0.5 ns
DLL Timing
t
KC Var
t
KC Var
Clock phase jitter – 0.20 ns
t
KC lock
t
KC lock
DLL lock time (K) 10240 – Cycles
t
KC Reset
t
KC Reset
K static to DLL reset 30 – ns
Notes
29. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V
DDQ
= 1.5 V,
input pulse levels of 0.25 V to 1.25 V, and output loading of the specified I
OL
/I
OH
and load capacitance shown in (a) of Figure 5 on page 24.
30. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is
being operated and outputs data with the output timings of that frequency range.
31. This part has a voltage regulator internally; t
POWER
is the time that the power must be supplied above V
DD(minimum)
initially before initiating a read or write operation.
32. These parameters are extrapolated from the input timing parameters (t
KHKH
– 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
KC Var
) is already
included in the t
KHKH
). These parameters are only guaranteed by design and are not tested in production.
33. t
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of Figure 5 on page 24. Transition is measured 100 mV from steady state voltage.
34. At any voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.
35. t
QVLD
Spec is applicable for both rising and falling edges of QVLD signal.
