NCP1380
www.onsemi.com
20
SHORT−CIRCUIT OR OVERLOAD MODE
Figure 37 shows the implementation of the fault timer.
ZCD/OPP
Laux
S
R
Q
Q
CS
Rsense
LEB1
+
−
S
R
Q
Q
Soft−start
VCC
au x
V
CC
management
latch
Vd d
fau l t
grand
reset
grand
reset
DRV
Soft−s t art end ?
then 1
else 0
IpFlag
+
−
SS en d
PW Mr eset
Up
Down
TIMER
Reset
VCCstop
FB/4
A&C:
OPP
V
ILIM IT
+
−
LEB2
V
CS(stop)
CsStop
CsStop
Figure 37. Overload Detection Schematic
Latched
When the current in the MOSFET is higher than V
ILIM
/
R
sense
, “Max Ip” comparator trips and the digital timer starts
counting: the timer count is incremented each 10 ms. When
the current comes back within safe limits, “Max Ip”
comparator becomes silent and the timer count down: the
timer count is decremented each 10 ms. In normal overload
conditions the timer reaches its completion when it has
counted up 8 times 10 ms.
On B and D version, when the timers reaches its
completion, the circuit enter auto−recovery mode: the
circuit stops all operations and V
CC
decreases via the circuit
own consumption (I
CC1
). When V
CC
reaches V
CC(off)
, the
circuit goes in startup mode and restart switching. (see
Figure 38) This ensures a low duty−cycle burst operation in
fault mode.
On A and C versions, when the timers finishes counting
80 ms, the circuit goes in latch mode (Figure 39): the DRV
pulses stop and V
CC
is pulled down to V
CC(latch)
which is
7.2 V typically. The circuit un−latches when the current
circulating in V
CC
pin drops below I
CC(latch)
.
In parallel to the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (t
BCS
) and a
threshold of 1.2 V is able to sense winding short−circuit and
immediately shut down the controller. Depending on the
version, this additional protection is either latched or
auto−recovery, according to the overload protection
behavior.
