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NCP1380BDR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
NCP1380
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22
OVER POWER COMPENSATION
The over power compensation is achieved by monitoring
the signal on ZCD pin (pin 1). Indeed, a negative voltage
applied on this pin directly affects the internal voltage
reference setting the maximum peak current (Figure 40).
When the power MOSFET is turned−on, the auxiliary
winding voltage becomes a negative voltage proportional to
the input voltage. As the auxiliary winding is already
connected to ZCD pin for the valley detection, by selecting
the right values for R
opu
and R
opl
, we can easily perform
over power compensation.
ZCD/OPP
ESD
protection
Aux
Ropu
Ropl
1
Rzcd
CS
+
−
Vth
DRV
Tblank
leakage blanking
Demag
OPP
V
ILIMIT
IpFlag
Figure 40. Over Power Compensation Circuit
To ensure optimal zero−crossing detection, a diode is
needed to bypass R
opu
during the off−time.
If we apply the resistor divider law on the pin 1 during the
on−time, we obtain the following relationship:
R
ZCD
) R
opu
R
opl
+*
N
p,aux
V
in
* V
OPP
V
OPP
(eq. 2)
Where:
N
p,aux
is the auxiliary to primary turn ration: N
p,aux
= N
aux
/ N
p
V
in
is the DC input voltage
V
OPP
is the negative OPP voltage
By selecting a value for R
opl
, we can easily deduce R
opu
using Equation 2. While selecting the value for R
opl
, we
must be careful not choosing a too low value for this resistor
in order to have enough voltage for zero−crossing detection
during the off−time. We recommend having at least 8 V on
ZCD pin, the maximum voltage being 10 V.
During the off−time, ZCD pin voltage can be expressed as
follows:
V
ZCD
+
R
opl
R
ZCD
) R
opl
ǒ
V
aux
* V
d
Ǔ
(eq. 3)
We can thus deduce the relationship between R
opl
and
R
ZCD
:
R
ZCD
R
opl
+
V
aux
* V
d
* V
ZCD
V
ZCD
(eq. 4)
Design example:
V
aux
= 18 V
V
d
= 0.6 V
N
p,aux
= 0.18
If we want at least 8 V on ZCD pin, we have:
R
ZCD
R
opl
+
V
aux
* V
d
* V
ZCD
V
ZCD
(eq. 5)
+
18 * 0.6 * 8
8
[ 1.2
We can choose: R
ZCD
= 1 kW and R
opl
= 1 kW.
For the over power compensation, we need to decrease the
peak current by 37.5% at high line (370 Vdc). The
corresponding OPP voltage is:
V
OPP
+ 0.375 V
ILIM
+ −300 mV
(eq. 6)
Using Equation 2, we have:
R
ZCD
) R
opu
R
opt
+*
N
p,aux
V
lin
* V
OPP
V
OPP
(eq. 7)
+
−0.18 370 *
(
−0.3
)
(
−0.3
)
+ 221
Thus,
R
opu
+ 221
Ropl
* R
ZCD
+ 221 1k * 1k + 220 kW
(eq. 8)
NCP1380
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23
OVERVOLTAGE/OVERTEMPERATURE DETECTION (A AND B VERSIONS)
Overvoltage and overtemperature detection is achieved
by reading the voltage on pin 7 (See Figure 41).
S
R
Q
Q
grand
reset
Fa ult
VCC
I
OTP(REF)
VDD
+
−
+
−
SS end
nois e de lay
nois e de lay
7
OTPc omp
OVPcomp
Rcl a mp
Vclam p
Clamp
Latch
OTP
V
OVP
V
NTC
Dz
Figure 41. OVP/OTP Circuitry
The I
OTP(REF)
current (91 mA typ.) biases the Negative
Temperature Coefficient sensor (NTC), naturally imposing
a dc voltage on the OTP pin. An internal clamp limit the
pin 7 voltage to 1.2 V when the NTC resistance is high (For
example, at 25°C, R
NTC
> 100 kW). When the temperature
increases, the NTC’s resistance reduces bringing the pin 7
voltage down until it reaches a typical value of 0.8 V: the
comparator trips and latches−off the controller (see
Figure 42).
In case of overvoltage, the zener diode starts to conduct
and inject current inside the internal clamp resistor R
clamp
thus causing the pin 7 voltage to increase. When this voltage
reaches the OVP threshold (2.5 V typ), the controller is
latched−off: all the DRV pulses stops and V
CC
is
pulled−down to V
CC(latch)
(7.2 V typ). The circuit
un−latches when the current circulating in V
CC
pin drops
below I
CC(latch)
, thus the user must unplug and replug the
power supply.
Figure 42. Overvoltage and Overtemperature Chronograms
NCP1380
www.onsemi.com
24
OVERVOLTAGE PROTECTION/BROWN−OUT (C AND D VERSIONS)
The C and D versions of NCP1380 combine brown−out
and overvoltage detection on pin 7.
S
R
Q
Q
VCC
S
R
Q
Q
gra nd
reset
DRV
OVP/BO
HV−Bulk
+
−
IBO
nois e del ay
VBO
BO reset
+
−
Vclamp
VOVP
nois e del ay
Rcl a mp
CS c omp
Rbou
Rbol
Dz
VDD
Latc h
Clamp
7
Figure 43. Brown−out and Overvoltage Protection
In order to protect the power supply against low input
voltage condition, the pin 7 permanently monitors a fraction
of the bulk voltage through a voltage divider. When this
image of bulk voltage is below the V
BO
threshold, the
controller stops switching. When the bulk voltage comes
back within safe limits, the circuit will restart pulsing only
when V
CC
reaches V
CC(on)
(Figure 44): this ensures a clean
startup sequence with soft−start. The hysteresis for the
brown−out function is implemented with a high side current
source sinking 10 mA when the brown−out comparator is
high (V
bulk
< V
bulk(on)
)
Figure 44. Brown−out Operating Chronograms
In order to avoid having a too high voltage on pin 7 if the
bulk voltage is high, an internal clamp limits the voltage.
In case of overvoltage, the zener diode will start to
conduct and inject current inside the internal clamp resistor
R
clamp
thus causing pin 7 voltage to increase. When this
voltage reaches V
OVP
, the controller latches−off and stays
latched until the user cycles down the power supply
(Figure 45).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

NCP1380BDR2G

Mfr. #:
Buy NCP1380BDR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers QUASI-RES CUR MODE CONTRL
Lifecycle:
New from this manufacturer.
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