ADP3629/ADP3630/ADP3631
Rev. 0 | Page 13 of 16
THERMAL CONSIDERATIONS
When designing a power MOSFET gate drive, the maximum
power dissipation in the driver must be considered to avoid
exceeding the maximum junction temperature.
Data on package thermal resistance is provided in Table 3 to
help the designer in this task.
Several equally important aspects must also be considered.
• Gate charge of the power MOSFET being driven
• Bias voltage value used to power the driver
• Maximum switching frequency of operation
• Value of external gate resistance
• Maximum ambient (and PCB) temperature
• Type of package
All of these factors influence and limit the maximum allowable
power dissipated in the driver.
The gate of a power MOSFET has a nonlinear capacitance
characteristic. For this reason, although the input capacitance
is usually reported in the MOSFET data sheet as C
ISS
, it is not
useful to calculate power losses.
The total gate charge necessary to turn on a power MOSFET
device is usually reported on the device data sheet under Q
G
.
This parameter varies from a few nanocoulombs (nC) to several
hundreds of nC and is specified at a specific V
GS
value (10 V
or 4.5 V).
The power necessary to charge and then discharge the gate of a
power MOSFET can be calculated as follows:
P
GATE
= V
GS
× Q
G
× f
SW
where:
V
GS
is the bias voltage powering the driver (V
DD
).
Q
G
is the total gate charge.
f
SW
is the maximum switching frequency.
The power dissipated for each gate (P
GATE
) must be multiplied
by the number of drivers (in this case, 1 or 2) being used in each
package; this P
GATE
value represents the total power dissipated in
charging and discharging the gates of the power MOSFETs.
Not all of this power is dissipated in the gate driver because
part of it is actually dissipated in the external gate resistor, R
G
.
The larger the external gate resistor, the smaller the amount of
power that is dissipated in the gate driver.
In modern switching power applications, the value of the gate
resistor is kept at a minimum to increase switching speed and
to minimize switching losses.
In all practical applications where the external resistor is in the
order of a few ohms, the contribution of the external resistor
can be ignored, and the extra loss is assumed to be in the driver,
providing a good guard band for the power loss calculations.
In addition to the gate charge losses, there are also dc bias losses
(P
DC
) due to the bias current of the driver. This current is present
regardless of the switching frequency.
P
DC
= V
DD
× I
DD
The total estimated loss is the sum of P
DC
and P
GATE
.
P
LOSS
= P
DC
+ (n × P
GATE
)
where n is the number of gates driven.
When the total power loss is calculated, the temperature
increase can be calculated as follows:
ΔT
J
= P
LOSS
× θ
JA
Design Example
For example, consider driving two IRFS4310Z MOSFETs with a
V
DD
of 12 V at a switching frequency of 100 kHz, using an
ADP3630 in the MSOP package.
The maximum PCB temperature considered for this design is 85°C.
From the MOSFET data sheet, the total gate charge is Q
G
= 120 nC.
P
GATE
= 12 V × 120 nC × 100 kHz = 144 mW
P
DC
= 12 V × 1.2 mA = 14.4 mW
P
LOSS
= 14.4 mW + (2 × 144 mW) = 302.4 mW
The MSOP thermal resistance is 162.2°C/W (see Table 3).
ΔT
J
= 302.4 mW × 162.2°C/W = 49.0°C
T
J
= T
A
+ ΔT
J
= 134.0°C ≤ T
J_MAX
This estimated junction temperature does not factor in the
power dissipated in the external gate resistor and, therefore,
provides a certain guard band.
If a lower junction temperature is required by the design,
the SOIC_N package, which provides a thermal resistance
of 110.6°C/W, can be used. Using the SOIC_N package, the
maximum junction temperature is
ΔT
J
= 302.4 mW × 110.6°C/W = 33.4°C
T
J
= T
A
+ ΔT
J
= 118.4°C ≤ T
J_MAX
Other options to reduce power dissipation in the driver include
reducing the value of the V
DD
bias voltage, reducing the switching
frequency, and choosing a power MOSFET with a smaller gate
charge.
