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ADP3631ARMZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
ADP3629/ADP3630/ADP3631
Rev. 0 | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SD
1
INA
2
PGND
3
INB
4
OTW
8
OUTA
7
VDD
6
OUTB
5
ADP3629
TOP VIEW
(Not to Scale)
08401-008
Figure 7. ADP3629 Pin Configuration
Table 4. ADP3629 Pin Function Descriptions
Pin No. Mnemonic Description
1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
2
INA
Inverting Input Pin for Channel A Gate Driver.
3 PGND Ground. This pin should be closely connected to the source of the power MOSFET.
4
INB
Inverting Input Pin for Channel B Gate Driver.
5 OUTB Output Pin for Channel B Gate Driver.
6 VDD Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor.
7 OUTA Output Pin for Channel A Gate Driver.
8
OTW
Overtemperature Warning Flag. Open drain, active low.
SD
1
INA
2
PGND
3
INB
4
OTW
8
OUTA
7
VDD
6
OUTB
5
ADP3630
TOP VIEW
(Not to Scale)
08401-001
Figure 8. ADP3630 Pin Configuration
Table 5. ADP3630 Pin Function Descriptions
Pin No. Mnemonic Description
1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
2 INA Input Pin for Channel A Gate Driver.
3 PGND Ground. This pin should be closely connected to the source of the power MOSFET.
4 INB Input Pin for Channel B Gate Driver.
5 OUTB Output Pin for Channel B Gate Driver.
6 VDD Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor.
7 OUTA Output Pin for Channel A Gate Driver.
8
OTW
Overtemperature Warning Flag. Open drain, active low.
SD
1
INA
2
PGND
3
INB
4
OTW
8
OUTA
7
VDD
6
OUTB
5
ADP3631
TOP VIEW
(Not to Scale)
08401-009
Figure 9. ADP3631 Pin Configuration
Table 6. ADP3631 Pin Function Descriptions
Pin No. Mnemonic Description
1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
2
INA
Inverting Input Pin for Channel A Gate Driver.
3 PGND Ground. This pin should be closely connected to the source of the power MOSFET.
4 INB Input Pin for Channel B Gate Driver.
5 OUTB Output Pin for Channel B Gate Driver.
6 VDD Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor.
7 OUTA Output Pin for Channel A Gate Driver.
8
OTW
Overtemperature Warning Flag. Open drain, active low.
ADP3629/ADP3630/ADP3631
Rev. 0 | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
3
4
5
6
7
8
9
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
UVLO (V)
V
UVLO_ON
V
UVLO_OFF
08401-022
Figure 10. UVLO vs. Temperature
0
2
4
6
8
10
12
14
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
t
FALL
t
RISE
TIME (ns)
08401-010
Figure 11. Rise and Fall Times vs. Temperature
0
10
20
30
40
50
60
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
TIME (ns)
V
DD
= 12V
t
dH_SD
t
dL_SD
t
D2
t
D1
08401-011
Figure 12. Propagation Delay vs. Temperature
0
5
10
15
20
25
0 5 10 15 20
V
DD
(V)
TIME (ns)
t
FALL
t
RISE
08401-012
Figure 13. Rise and Fall Times vs. V
DD
0
10
20
30
40
50
60
70
0 5 10 15 20
t
dL_SD
t
D2
t
D1
t
dH_SD
V
DD
(V)
TIME (ns)
08401-013
Figure 14. Propagation Delay vs. V
DD
0
200
400
600
800
1000
1200
1400
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
SHUTDOWN THRESHOLD (mV)
V
SD_H
V
SD_L
V
SD_HYST
0
8401-014
Figure 15. Shutdown Threshold vs. Temperature
ADP3629/ADP3630/ADP3631
Rev. 0 | Page 9 of 16
1
2
OUTA/OUTB
INA/INB
V
DD
= 12V
TIME = 20ns/DIV
08401-023
Figure 16. Typical Rising Propagation Delay (Noninverting)
1
2
V
DD
= 12V
TIME = 20ns/DIV
OUTA/OUTB
INA/INB
08401-024
Figure 17. Typical Falling Propagation Delay (Noninverting)
1
2
V
DD
= 12V
TIME = 20ns/DIV
OUTA/OUTB
INA/INB
08401-025
Figure 18. Typical Rise Time (Noninverting)
1
2
V
DD
= 12V
TIME = 20ns/DIV
OUTA/OUTB
INA/INB
08401-026
Figure 19. Typical Fall Time (Noninverting)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADP3631ARMZ-R7

Mfr. #:
Buy ADP3631ARMZ-R7
Manufacturer:
Analog Devices Inc.
Description:
Gate Drivers High Speed Dual 2A MOSFET Dvr
Lifecycle:
New from this manufacturer.
Delivery:
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