4
FN8191.4
January 15, 2009
Principals of Operation
The X9408 is a highly integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the XDCP
potentiometers.
Serial Interface
The X9408 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9408 will be
considered a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t
LOW
). SDA state changes during SCL HIGH
are reserved for indicating start and stop conditions.
Start Condition
All commands to the X9408 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (t
HIGH
). The X9408 continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9408 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9408 will
respond with a final acknowledge.
Array Description
The X9408 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (R
H
and
R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R
W
)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The six bits of the WCR are
decoded to select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant four
bits of the slave address are the device type identifier (refer
to Figure 1 below). For the X9408 this is fixed as 0101[B].
The next four bits of the slave address are the device
address. The physical device address is defined by the state
of the A
0
- A
3
inputs. The X9408 compares the serial data
stream with the address input state; a successful compare of
all four address bits is required for the X9408 to respond with
an acknowledge. The A
0
- A
3
inputs can be actively driven
by CMOS input signals or tied to V
CC
or V
SS
.
Acknowledge Polling
The disabling of the inputs, during the internal Nonvolatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the nonvolatile write command
the X9408 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the X9408
is still busy with the write operation no ACK will be returned.
If the X9408 has completed the write operation an ACK will
be returned and the master can then proceed with the next
operation.
100
A3 A2 A1 A0
DEVICE TYPE
IDENTIFIER
DEVICE ADDRESS
1
FIGURE 1. SLAVE ADDRESS
X9408
5
FN8191.4
January 15, 2009
Flow 1. ACK Polling Sequence
Instruction Structure
The next byte sent to the X9408 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next four bits point to one of the two pots
and when applicable they point to one of four associated
registers. The format is shown in Figure 2.
The four high order bits define the instruction. The next two
bits (R1 and R0) select one of the four registers that is to be
acted upon when a register oriented instruction is issued.
The last bits (P1, P0) select which one of the four
potentiometers is to be affected by the instruction.
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the Data
Registers. A transfer from a Data Register to a Wiper
Counter Register is essentially a write to a static RAM. The
response of the wiper to this action will be delayed t
WRL
. A
transfer from the Wiper Counter Register (current wiper
position), to a data register is a write to nonvolatile memory
and takes a minimum of t
WR
to complete. The transfer can
occur between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein the
transfer occurs between all of the potentiometers and one of
their associated registers.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9408; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register.
These instructions are: Read Wiper Counter Register (read
the current wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents of the
selected nonvolatile register) and Write Data Register (write
a new value to the selected Data Register). The sequence of
operations is shown in Figure 4.
NON-VOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ACK
RETURNED?
FURTHER
OPERATION?
ISSUE
INSTRUCTION
ISSUE STOP
NO
YES
YES
PROCEED
ISSUE STOP
NO
PROCEED
I1I2I3 I0 R1 R0 P1 P0
WIPER COUNTER
REGISTER
SELECT
INSTRUCTIONS
REGISTER SELECT
FIGURE 2. INSTRUCTION BYTE FORMAT
S
T
A
R
T
0101A3A2A1A0
A
C
K
I3 I2 I1 I0 R1 R0 P1 P0
A
C
K
SCL
SDA
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
X9408
6
FN8191.4
January 15, 2009
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9408 has responded with an acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t
HIGH
) while SDA is HIGH, the
selected wiper will move one resistor segment towards the
R
H
terminal. Similarly, for each SCL clock pulse while SDA is
LOW, the selected wiper will move one resistor segment
towards the R
L
terminal. A detailed illustration of the
sequence and timing for this operation are shown in Figures
5 and 6 respectively.
TABLE 1. INSTRUCTION SET
NOTE: (7)1/0 = data is one or zero
INSTRUCTION
INSTRUCTION SET
OPERATIONI
3
I
2
I
1
I
0
R
1
R
0
P
1
P
0
Read Wiper CounterRegister 1 0 0 1 0 0 P
1
P
0
Read the contents of the Wiper Counter Register pointed to by
P
1
- P
0
Write Wiper CounterRegister 1 0 1 0 0 0 P
1
P
0
Write new value to the Wiper Counter Register pointed to by P
1
- P
0
Read Data Register 1 0 1 1 R
1
R
0
P
1
P
0
Read the contents of the Data Register pointed to by P
1
- P
0
and
R
1
- R
0
Write Data Register 1 1 0 0 R
1
R
0
P
1
P
0
Write new value to the Data Register pointed to by
P
1
- P
0
and R
1
- R
0
XFR Data Register to Wiper
Counter Register
1101R
1
R
0
P
1
P
0
Transfer the contents of the Data Register pointed to by P
1
- P
0
and R
1
- R
0
to its associated Wiper Counter Register
XFR Wiper Counter Register
to Data Register
1110R
1
R
0
P
1
P
0
Transfer the contents of the Wiper Counter Register pointed to by
P
1
- P
0
to the Data Register pointed to by R
1
- R
0
Global XFR Data Registers
to Wiper Counter Registers
0001R
1
R
0
0 0 Transfer the contents of the Data Registers pointed to by R
1
- R
0
of all four pots to their respective Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
1000R
1
R
0
0 0 Transfer the contents of both Wiper Counter Registers to their
respective Data Registers pointed to by
R
1
- R
0
of all four pots
Increment/Decrement Wiper
Counter Register
001000P
1
P
0
Enable Increment/decrement of the Wiper Counter Register
pointed to by P
1
- P
0
S
T
A
R
T
0 1 0 1 A3 A2 A1 A0 A
C
K
I3 I2 I1 I0 R1 R0 P1 P0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
0 0 D5 D4 D3 D2 D1 D0
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
S
T
A
R
T
0 1 0 1 A3 A2 A1 A0
A
C
K
I3 I2 I1 I0 R0 P1 P0 A
C
K
SCL
SDA
S
T
O
P
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
R1
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
X9408

X9408WV24Z-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs DL CMOS EEPOT 10KOHM S
Lifecycle:
New from this manufacturer.
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