CS5157H
http://onsemi.com
7
The V
2
control method is illustrated in Figure 3. The output
voltage is used to generate both the error signal and the ramp
signal. Since the ramp signal is simply the output voltage, it is
affected by any change in the output regardless of the origin of
that change. The ramp signal also contains the DC portion of
the output voltage, which allows the control circuit to drive the
main switch to 0% or 100% duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V
2
control
scheme to compensate the duty cycle. Since the change in
inductor current modifies the ramp signal, as in current mode
control, the V
2
control scheme has the same advantages in line
transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls the
main switch. Load transient response is determined only by the
comparator response time and the transition speed of the main
switch. The reaction time to an output load step has no relation
to the crossover frequency of the error signal loop, as in
traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this ‘slow’ feedback loop is to provide
DC accuracy. Noise immunity is significantly improved, since
the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote sensing
of the output voltage, since the noise associated with long
feedback traces can be effectively filtered.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compensate for
a deviation in either line or load voltage. This change in the error
signal causes the output voltage to change corresponding to the
gain of the error amplifier, which is normally specified as line
and load regulation. A current mode controller maintains fixed
error signal under deviation in the line voltage, since the slope
of the ramp signal changes, but still relies on a change in the
error signal for a deviation in load. The V
2
method of control
maintains a fixed error signal for both line and load variation,
since the ramp signal is affected by both line and load.
Constant Off Time
To maximize transient response, the CS5157H uses a
constant off time method to control the rate of output pulses.
During normal operation, the off time of the high side switch
is terminated after a fixed period, set by the C
OFF
capacitor. To
maintain regulation, the V
2
control loop varies switch on time.
The PWM comparator monitors the output voltage ramp, and
terminates the switch on time.
Constant off time provides a number of advantages. Switch
duty cycle can be adjusted from 0 to 100% on a pulse by pulse
basis when responding to transient conditions. Both 0% and
100% duty cycle operation can be maintained for extended
periods of time in response to load or line transients. PWM
slope compensation to avoid sub−harmonic oscillations at high
duty cycles is avoided.
Switch on time is limited by an internal 25 ms timer,
minimizing stress to the power components.
Programmable Output
The CS5157H is designed to provide two methods for
programming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges. The
first range is 2.10 V to 3.50 V in 100 mV steps, the second is
1.30 V to 2.05 V in 50 mV steps, depending on the digital
input code. If all five bits are left open, the CS5157H enters
adjust mode. In adjust mode, the designer can choose any
output voltage by using resistor divider feedback to the V
FB
and V
FFB
pins, as in traditional controllers.
Startup
Until the voltage on the V
CC1
supply pin exceeds the 3.9 V
monitor threshold, the Soft−Start and gate pins are held low.
The FAULT latch is reset (no Fault condition). The output of
the error amplifier (COMP) is pulled up to 1.0 V by the
comparator clamp. When the V
CC1
pin exceeds the monitor
threshold, the GATE(H) output is activated, and the
Soft−Start capacitor begins charging. The GATE(H) output
will remain on, enabling the NFET switch, until terminated
by either the PWM comparator, or the maximum on time
timer.
If the maximum on time is exceeded before the regulator
output voltage achieves the 1.0 V level, the pulse is
terminated. The GATE(H) pin drives low, and the GATE(L)
pin drives high for the duration of the extended off time. This
time is set by the time out timer and is approximately equal
to the maximum on time, resulting in a 50% duty cycle. The
GATE(L) pin will then drive low, the GATE(H) pin will drive
high, and the cycle repeats.
When regulator output voltage achieves the 1.0 V level
present at the COMP pin, regulation has been achieved and
normal off time will ensue. The PWM comparator terminates
the switch on time, with off time set by the C
OFF
capacitor.
The V
2
control loop will adjust switch duty cycle as required
to ensure the regulator output voltage tracks the output of the
error amplifier.
The Soft−Start and COMP capacitors will charge to their
final levels, providing a controlled turn on of the regulator
output. Regulator turn on time is determined by the COMP
capacitor charging to its final value. Its voltage is limited by
the Soft−Start COMP clamp and the voltage on the Soft−Start
pin (see Figures 4 and 5).
