LT1976/LT1976B
24
1976bfg
APPLICATIO S I FOR ATIO
WUUU
Board layout also has a significant effect on thermal
resistance. Pin 8 and the exposed die pad, Pin 17, are a
continuous copper plate that runs under the LT1976 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pin 8 and exposed
pad onto the board will reduce die temperature and in-
crease the power capability of the LT1976. This is achieved
by providing as much copper area as possible around the
exposed pad. Adding multiple solder filled feedthroughs
under and around this pad to an internal ground plane will
also help. Similar treatment to the catch diode and coil
terminations will reduce any additional heating effects.
THERMAL CALCULATIONS
Power dissipation in the LT1976 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
P
RI V
V
tIVf
SW
SW OUT OUT
IN
EFF OUT IN
=
()( )
+
()
()()()
2
12/
Boost current loss:
P
VI
V
BOOST
OUT OUT
IN
=
()
()
2
36/
Quiescent current loss: (LT1976)
P
Q
= V
IN
(0.0015) + V
OUT
(0.003)
R
SW
= switch resistance (≈0.3 when hot )
t
EFF
= effective switch current/voltage overlap time
(t
r
+ t
f
+ t
IR
+ t
IF
)
t
r
= (V
IN
/1.7)ns
t
f
= (V
IN
/1.2)ns
t
IR
= t
IF
= (I
OUT
/0.05)ns
f = switch frequency
Example: with V
IN
= 40V, V
OUT
= 5V and I
OUT
= 1A:
Pee
W
PW
PW
SW
BOOST
Q
=
()()()
+
()
()
()( )( )
+=
=
()
()
=
=
()
+
()
=
03 1 5
40
97 9 1 2 1 40 200 3
004 0388 043
5136
40
002
40 0 0015 5 0 003 0 08
2
2
.
–/
.. .
/
.
...
Total power dissipation is:
P
TOT
= 0.43 + 0.02 + 0.08 = 0.53W
Thermal resistance for the LT1976 package is influenced
by the presence of internal or backside planes. With a full
plane under the FE16 package, thermal resistance will be
about 45°C/W. No plane will increase resistance to about
150°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
T
J
= T
A
+ Q
JA
(P
TOT
)
With the FE16 package (Q
JA
= 45°C/W) at an ambient
temperature of 70°C:
T
J
= 70 + 45(0.53) = 94°C
If a more accurate die temperature is required, a measure-
ment of the SYNC pin resistance to ground can be used.
The SYNC pin resistance can be measured by forcing a
voltage no greater than 0.25V at the pin and monitoring the
pin current versus temperature in a controlled temperature
environment. The measurement should be done with
minimal device power dissipation (pull the V
C
pin to
ground for sleep mode) in order to calibrate the SYNC pin
resistance with the ambient temperature.
