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NCP5425DB

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NCP5425
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16
where:
I
RMS(H)
= maximum switching MOSFET RMS current;
I
L(PEAK)
= inductor peak current;
I
L(VALLEY)
= inductor valley current;
D = duty cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated by:
P
RMS(H)
+ I
RMS(H)
2
R
DS(ON)
where:
P
RMS(H)
= switching MOSFET conduction losses;
I
RMS(H)
= maximum switching MOSFET RMS current;
R
DS(ON)
= FET drain−to−source on−resistance.
Upper MOSFET switching losses occur during MOSFET
switch−on and switch−off, and can be calculated by:
P
SWH
+ P
SWH(ON)
) P
SWH(OFF)
+
V
IN
I
OUT
(t
RISE
) t
FALL
)
6T
where:
P
SWH(ON)
= upper MOSFET switch−on losses;
P
SWH(OFF)
= upper MOSFET switch−off losses;
V
IN
= input voltage;
I
OUT
= load current;
T
RISE
=MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
TFALL = MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
T = 1/f
SW
= period.
The total power dissipation in the switching MOSFET can
then be calculated as:
P
HFET(TOTAL)
+ P
RMS(H)
) P
SWH(ON)
) P
SWH(OFF)
where:
P
HFET(TOTAL)
= total switching (upper) MOSFET losses;
P
RMS(H)
= upper MOSFET switch conduction Losses;
P
SWH(ON)
= upper MOSFET switch−on losses;
P
SWH(OFF)
= upper MOSFET switch−off losses.
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
T
J
+ T
A
)
[
P
HFET(TOTAL)
R
qJA
]
where:
T
J
= FET junction temperature;
T
A
= ambient temperature;
P
HFET(TOTAL)
= total switching (upper) FET losses;
R
qJA
= upper FET junction−to−ambient thermal
resistance.
Synchronous (Lower) FET Selection
The switch conduction losses for the lower FET are
calculated as follows:
P
RMS(L)
+ I
RMS
2
R
DS(ON)
+
ƪ
I
OUT
(1 * D)
Ǹ
ƫ
2
R
DS(ON)
where:
P
RMS(L)
= lower MOSFET conduction losses;
I
OUT
= load current;
D = Duty Cycle;
R
DS(ON)
= lower FET drain−to−source on−resistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non−overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
P
SWL
+ V
SD
I
LOAD
non−overlap time f
SW
where:
P
SWL
= lower FET switching losses;
V
SD
= lower FET source−to−drain voltage;
I
LOAD
= load current;
Non−overlap time = GATE(L)−to−GATE(H) or
GATE(H)−to−GATE(L) delay
(from NCP5425 data sheet
Electrical Characteristics section);
f
SW
= switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
P
LFET(TOTAL)
+ P
RMS(L)
) P
SWL
where:
P
LFET(TOTAL)
= Synchronous (lower) FET total losses;
P
RMS(L)
= Switch Conduction Losses;
P
SWL
= Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
T
J
+ T
A
) [P
LFET(TOTAL)
R
qJA
]
where:
T
J
= MOSFET junction temperature;
T
A
= ambient temperature;
P
LFET(TOTAL)
= total synchronous (lower) FET losses;
R
qJA
= lower FET junction−to−ambient thermal
resistance.
NCP5425
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Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, VCC, and the NCP5425 operating frequency. The
average MOSFET gate charge current typically dominates
the control IC power dissipation, and is given by:
P
CONTROL(IC)
+ I
CC1
V
CC1
) I
BST
V
BST
) P
GATE(H)1
) P
GATE(L)1
) P
GATE(H)2
) P
GATE(L)2
where:
P
CONTROL(IC)
= control IC power dissipation;
I
CC1
= IC quiescent supply current;
V
CC1
= IC supply voltage;
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
P
GATE(L)
= lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses
are given by:
P
GATE(H)
+ Q
GATE(H)
f
SW
V
BST
where:
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
Q
GATE(H)
= total upper MOSFET gate charge at VCC;
f
SW
= switching frequency.
The lower (synchronous) MOSFET gate driver (IC)
losses are:
P
GATE(L)
+ Q
GATE(L)
f
SW
V
CC
where:
P
GATE(L)
= lower MOSFET gate driver (IC) losses;
Q
GATE(L)
= total lower MOSFET gate charge at VCC;
f
SW
= switching frequency.
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
CURRENT SENSING AND CURRENT SHARING
Current Sharing Errors
The three main errors in current are from board layout
imbalances, inductor mismatch, and input offsets in the error
amplifiers. The first two sources of error can be controlled
through careful component selection and good layout
practice. With a 4.0 mW (parasitic winding resistance)
inductor, for example, one mV of input offset error will
represent 0.25 A of measurement error. One way to diminish
this effect is to use higher resistance inductors, but the
penalty is higher power losses in the inductors.
Current Limiting Options
The current supplied to the load can be sensed using the
IS+ and IS− pins. These pins sense a voltage, proportional
to the output current, and compare it to a fixed internal
voltage threshold. When the differential voltage exceeds
70 mV, the internal overcurrent protection system goes into
a cycle−by−cycle limiting mode. Two methods for sensing
the current are available.
Sense Resistor
A sense resistor can be added in series with the inductor.
When the voltage drop across the sense resistor exceeds the
internal voltage threshold of 70 mV, a limit condition is set.
The sense resistor value is calculated by:
R
SENSE
+
0.070 V
I
LIMIT
In a high current supply, the sense resistor will be a very
low value, typically less than 10 mW. Such a resistor can be
either a discrete component or a PCB trace. The resistance
of a discrete component can be more precise than a PCB
trace, but the cost is also greater. Setting the current limit
using an external sense resistor is very precise because all
the values can be designed to specific tolerances. However,
the disadvantage of using a sense resistor is its additional
constant power loss and heat generation. Trace resistance
can vary as much as "10% due to copper plating variations.
Inductor ESR
Another means of sensing current is to use the intrinsic
resistance of the inductor. A model of an inductor reveals
that the windings have an effective series resistance (ESR).
The voltage drop across the inductor ESR can be measured
with a simple parallel circuit: an RC integrator. If the value
of RS1 and C are chosen such that:
L
ESR
+ R
S1
C
then the voltage measured across the capacitor C will be:
V
C
+ ESR I
LIM
Inductor Sensing Component Selection
Select the capacitor C first. A value of 0.1 mF is
recommended. The value of RS1 can be calculated by:
R
S1
+
L
ESR C
Typical values for inductor ESR range in the low
milliohms; consult manufacturer’s data sheets for specific
values. Selection of components at these values will result
in a current limit of:
I
LIM
+
0.070 V
ESR
Figure 11. Inductor ESR Current Sensing
V
CC
GATE(H)
GATE(L)
IS+
IS−
L ESR
RS1
C
Co
NCP5425
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Given an ESR value of 3.5 mW, the current limit becomes
20 A. If an increased current limit is required, a resistor
divider can be added (see Figure 8). Advantages of setting
the current limit by using the winding resistance of the
inductor (relative to a sense resistor) are higher efficiency
and lower heat generation. The tolerance of the inductor
ESR must be factored into the design of the current limit.
Finally, one or two more components are required for this
approach than with resistor sensing.
Selecting and Configuring Current Sharing for a 2
Phase Single Output Application
When the two controllers are connected as a single output
two phase Buck Converter, they are in a Master−Slave
configuration. The Slave controller on the right side of
Figure 6 tries to follow information provided by the Master
controller, on the left. This circuit uses inductor current
sensing, in which the parasitic resistances (LSR) of the
controllers’ output chokes are used as current sensing
elements. On the Slave side (Controller Two), both Error
Amplifier inputs are brought to external pins so the
reference is available. The RC network in parallel with the
output inductor on the Master side (Controller One)
generates the reference for the Slave. Current information
from the Slave is fed back to the error amplifier’s inverting
input. In this configuration, the Slave tries to adjust its
current to match the current information fed to its reference
input from the Master Controller. If 50−50 current sharing
is needed, then Figure 8a is used for both sides to generate
the reference and the inverting signals. The values for both
sides should be calculated with the following equation:
R1 +
Lx
C1 · Rx
,where,
L
x
=Inductor value, both controllers should use the same
inductor.
R
x
= Internal resistance of L, from the inductor data sheet.
C1 = Select a value such that R1 is less than 15 KW.
With the RC time constant selected to equal the L
x
/R
x
time
constant, the voltage across the capacitor will be equal to the
voltage drop across the internal resistance of the inductor.
For proper sharing, the inductors on both Master and Slave
side should be the identical.
If a current share ratio other than 50−50 is desired,
inductor sense resistor network selection is a three step
process:
1. Decide how the total load current will be budgeted
between the two controllers.
2. Calculate the value of R1 for the controller with
the lesser current share.
3. Calculate the current sense resistor network
(2 resistors) for the controller with the greater
current share.
In the two examples that follow, the inductor sense
resistors are designated R1, R2, and R3, as depicted in
Figures 12 and 13.
Figure 12. 40%/60% Current Sharing
Rx
Lx
Master
Switch
Node
R1
Slave
Error
Amp
R2
Rx
Lx
C1
DC
Output
R3
C1
Slave
Switch
Node
Figure 13. 66.7%/33.3% Current Sharing
Rx
Lx
Master
Switch
Node
R2
Slave
Error
Amp
R1
Rx
Lx
C1
DC
Output
R3
C1
Slave
Switch
Node
Example 1
Assume we have elected to source 40% of the output
current from the master controller, and 60% from the Slave.
Figure 12 shows the configuration of the inductor sense
networks and Slave error amplifier. The ratio of
Slave−to−Master load current is 60%/40%, or 1.5:1. R2 and
R3 must be chosen to satisfy two conditions:
A parallel equivalent resistance equal to R1, and,
A ratio such that the drop across the parasitic resistance of
the Slave inductor is 1.5 times the drop across the parasitic
resistance of the Master inductor when the inputs to the
Slave error amplifier are equal (assumes the inductors are
identical). The optimum value of R1 is described by the
equation:
R1 + Lxń(C1 * Rx)
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NCP5425DB

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Manufacturer:
ON Semiconductor
Description:
Switching Controllers Dual Synchronous
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