NCP5425DB Datasheet NCP5425DBR2G, NCP5425DB, NCP5425DBG | P19-P21

NCP5425

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The values of R2 and R3 can be found by solving two

simultaneous equations:

R2 + R3ń2

R1 + (R2 * R3)ń(R2 ) R3)

Solving for R2 and R3 yields:

R2 + 1.5R1

R3 + 3R1

Example 2

Assume we have elected to source 66.7% output current

from the Master controller, and 33.3% from the Slave.

Figure 13 shows the configuration of the inductor sense

networks and Slave error amplifier for this case. The ratio of

Master−to−Slave load current is equal to 66.7%/33.3%, or

2:1. Therefore R2 and R3 must be chosen to satisfy two

conditions:

A parallel equivalent resistance equal to R1, and,

A ratio such that the drop across the parasitic resistance of

the Master inductor is 2 times the drop across the parasitic

resistance of the Slave inductor when the inputs to the

Slave error amplifier are equal (assumes the inductors are

identical). The optimum value of R1 is described by the

equation:

R1 + Lxń(C1 * Rx)

The values of R2 and R3 can be found by solving two

simultaneous equations:

R2 + R3

R1 + (R2 * R3)ń(R2 ) R3)

Solving for R2 and R3 yields:

R2 + 2R1

R3 + 2R1

Note that the Mode pin must be floating for a two−phase,

single output design. This disables the internal Error

Amplifier Reference clamp, and increases its common mode

range.

No Load Zero Balance

To improve current matching, a low pass filter can be

inserted between the Master controller inductor sensing RC

network and the Slave controller Vref2 input pin (see

Figure 14). This will attenuate the amplitude of the

out−of−phase ripple current signal superimposed on the DC

current signal, providing a smoother Slave Error Amplifier

reference input.

Vin

R3R3

−

Vfb1

Master

Error Amp

Internal

0.8 V Ref.

−

Vfb2

Vref2

Low Pass

Filter

Slave

Error Amp

Figure 14. Addition of a Low Pass Filter to the Current Sense Reference Input

Vout

With the value of R

set to approximately two times the

value of R1, Cf can be calculated as follows:

Cf + 1ń(2p ·f·R

), where :

f = operating frequency of the controller

When a filter is added, the response delay introduced by

the RC time constant must be considered.

Configuring a Dual Output Application

To configure the NCP5425 for a dual output application:

• The Mode pin must be grounded

• An external voltage reference must be provided for

Controller 2, via the Vref2 pin

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Grounding the Mode pin enables an internal clamp to limit

the Comp 2 voltage excursions during overcurrent faults.

Without this clamp, the output voltage (Vout1 and Vout2)

can overshoot the regulated output voltages when the fault

is removed. For a single output two−phase application the

Mode pin must be floating, which disables the clamp and

permits a larger current−sharing reference voltage range.

The Comp1 pin is always clamped, because it is regulated to

a fixed internal voltage (0.8 V).

The simplest way to provide a Controller 2 reference is by

using the Controller 1 feedback voltage. This will provide a

0.8 V reference for regulation, and also causes the

Controller 2 output to track the Controller 1 output during

transients. With a voltage reference established and the

Mode pin floating, Controller 2 can function as an

independent Buck regulator.

Vin

−

Vfb1

Master

Error Amp

Internal

0.8 V Ref.

−

Vfb2

Vref2

Slave

Error Amp

Figure 15. Dual Output Configuration

Vref1

Vout1 Vout2

Adding External Slope Compensation

Today’s voltage regulators are expected to meet very

stringent load transient requirements. One of the key factors

in achieving tight dynamic voltage regulation is low ESR.

Low ESR at the regulator output results in low output

voltage ripple. The consequence is, however, that very little

voltage ramp exists at the control IC feedback pin (VFB),

resulting in increased regulator sensitivity to noise and the

potential for loop instability. In applications where the

internal slope compensation is insufficient, the performance

of the NCP5425−based regulator can be improved through

the addition of a fixed amount of external slope

compensation at the output of the PWM Error Amplifier (the

COMP pin) during the regulator off−time. Referring to

Figure 8, the amount of voltage ramp at the COMP pin is

dependent on the gate voltage of the lower (synchronous)

FET and the value of resistor divider formed by R1and R2.

SLOPECOMP

+ V

GATE(L)

R1 ) R2

(1−e

−1

)

where:

SLOPECOMP

= amount of slope added;

GATE(L)

= lower MOSFET gate voltage;

R1, R2 = voltage divider resistors;

t = t

or t

OFF

(switch off−time);

t = RC constant determined by C1 and the parallel

combination of R1, R2 neglecting the low driver

output impedance.

Figure 16. RC Filter Provides the Proper Voltage

Ramp at the Beginning of each On−Time Cycle

COMP

NCP5425

GATE(L)

To Synchronous

FET

The artificial voltage ramp created by the slope

compensation scheme results in improved control loop

stability provided that the RC filter time constant is smaller

than the off−time cycle duration (time during which the lower

MOSFET is conducting). It is important that the series

combination of R1 and R2 is high enough in resistance to

avoid loading the GATE(L) pin. Also, C1 should be very

small (less than a few nF) to avoid heating the part.

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EMI MANAGEMENT

As a consequence of large currents being turned on and off

at high frequency, switching regulators generate noise

during normal operation. When designing for compliance

with EMI/EMC regulations, additional components may be

necessary to reduce noise emissions. These components are

not required for regulator operation and experimental results

may allow them to be eliminated. The input filter inductor

may not be required because bulk filter and bypass

capacitors, as well as other loads located on the board will

tend to reduce regulator di/dt effects on the circuit board and

input power supply. Placement of the power components to

minimize routing distance will also help to reduce

emissions.

LAYOUT GUIDELINES

When laying out a buck regulator on a printed circuit

board, the following checklist should be used to ensure

proper operation of the NCP5425.

1. Rapid changes in voltage across parasitic capacitors

and abrupt changes in current in parasitic inductors

are major concerns.

2. Keep high currents out of sensitive ground

connections.

3. Avoid ground loops as they pick up noise. Use star

or single point grounding.

4. For high power buck regulators on double−sided

PCB’s a single ground plane (usually the bottom)

is recommended.

5. Even though double sided PCB’s are usually

sufficient for a good layout, four−layer PCB’s are

the optimum approach to reducing susceptibility to

noise. Use the two internal layers as the power and

GND planes, the top layer for power connections

and component vias, and the bottom layers for the

noise sensitive traces.

6. Keep the inductor switching node small by placing

the output inductor, switching and synchronous

FETs close together.

7. The MOSFET gate traces to the IC must be short,

straight, and wide as possible.

8. Use fewer, but larger output capacitors, keep the

capacitors clustered, and use multiple layer traces

with wide, thick copper to keep the parasitic

resistance low.

9. Place the switching MOSFET as close to the input

capacitors as possible.

10. Place the output capacitors as close to the load as

possible.

11. Place the COMP capacitor as close as possible to

the COMP pin.

12. Connect the filter components of pins ROSC, VFB,

VOUT, and COMP, to the GND pin with a single

trace, and connect this local GND trace to the

output capacitor GND.

13. Place the VCC bypass capacitors as close as possible

to the IC.

14. Place the ROSC resistor as close as possible to the

ROSC pin.

15. Assign the output with lower duty cycle to

channel 2, which has inherently better noise

immunity.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

NCP5425DB

Mfr. #:

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Switching Controllers Dual Synchronous

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NCP5425DB

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