NCP5425
http://onsemi.com
4
ELECTRICAL CHARACTERISTICS (0°C < T
J
< 125°C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1 mF, 4.75 V < V
CC
< 13.2 V;
10.8 V < BST < 20 V, C
GATE(H)1,2
= C
GATE(L)1,2
= 1.0 nF; unless otherwise specified.)
Characteristic Test Condition Min Typ Max Unit
ERROR AMPLIFIER
V
FB1
Input Bias Current V
FB1
= 0 V − 0.1 1.0
mA
V
FB2
, V
REF2
Input Bias Current V
FB2
, V
REF2
= 0.8 V − 0.1 1.0
mA
Common Mode Input Voltage Range − 0.3 − 1.0 V
COMP1(2) Source Current COMP1(2) = 1.2 V to 2.5 V; V
FB1(2)
= 0.6 V 15 30 60
mA
COMP1(2) Sink Current COMP1(2) = 1.2 V; V
FB1(2)
= 1.0 V 15 30 60
mA
Reference Voltage COMP1 = V
FB1
0.792 0.800 0.808 V
COMP1 Max Voltage
COMP2 Max Voltage, Mode Floating
COMP2 Max Voltage, Mode = 0
V
FB1(2)
= 0.6 V
V
FB1(2)
= 0.6 V
V
FB1(2)
= 0.6 V
−
3.0
−
2.0
3.1
2.0
2.1
−
2.1
V
COMP1(2) Min Voltage V
FB1(2)
= 1.2 V − 0.10 0.20 V
Open Loop Gain − 95 − dB
Unity Gain Bandwidth − 40 − kHz
PSRR @ 1.0 kHz − 70 − dB
Transconductance − − 32 − mmho
Output Impedance − − 2.5 −
MW
GATE(H) AND GATE(L)
High Voltage (AC) V
CC
− GATE(L)1,2
BST − GATE(H)1,2 (Note 2)
− 0 0.5 V
Low Voltage (AC) GATE(L)1,2 or GATE(H)1,2 (Note 2) − 0 0.5 V
Rise Time 1.0 V < GATE(L)1,2 < V
CC
− 1.0 V
1.0 V < GATE(H)1,2 < BST − 1.0 V
− 25 80 ns
Fall Time V
CC
− 1.0 > GATE(L)1,2 > 1.0 V
BST − 1.0 > GATE(H)1,2 > 1.0 V
− 25 80 ns
GATE(H) to GATE(L) Delay GATE(H)1,2 < 2.0 V
GATE(L)1,2 > 2.0 V
20 40 80 ns
GATE(L) to GATE(H) Delay GATE(L)1,2 < 2.0 V
GATE(H)1,2 > 2.0 V
20 40 80 ns
GATE(H)1(2) and GATE(L)1(2) Pull−Down Resistance to GND (Note 2) 50 125 280
kW
PWM COMPARATOR
Propagation Delay COMP1(2) = 1.0 V
V
FB1(2)
= 0 to 1.2 V (Note 2)
− 200 300 ns
PWM Comparator Offset V
FB1(2)
= 0 V; Increase COMP1(2) until
GATE(H)1(2) starts switching
0.20 0.30 0.45 V
Artificial Ramp Duty Cycle = 50% 55 95 150 mV
Minimum Pulse Width (Note 2) − 80 130 ns
2. Guaranteed by design, not 100% tested in production.
