16
LTC1703
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internal latch. This latch releases the pull-down at FAULT,
allowing the 10µA pull-up to take it high. When FAULT
goes high, the LTC1703 stops all switching, turns both QB
(bottom synchronous) MOSFETs on continuously and
remains in this state until both RUN/SS pins are pulled low
simultaneously, the power supply is recycled, or the
FAULT pin is pulled low externally. This behavior is
intended to protect a potentially expensive load from
overvoltage damage at all costs. Under some conditions,
this behavior can cause the output voltage to undershoot
below ground. If latched FAULT mode is used, a Schottky
diode should be added with its cathode at the output and
its anode at ground to clamp the negative voltage to a safe
level and prevent possible damage to the load and the
output capacitors.
Note that in overvoltage conditions, the MAX comparator
will kick in at just +5%, turning QB on continuously long
before the output reaches +15%. Under most fault condi-
tions, this is adequate to bring the output back down
without firing the fault latch. Additionally, if MAX success-
fully keeps the output below +15%, the LTC1703 will
resume normal regulation as soon as the output overvolt-
age fault is resolved.
In some circuits, the OV latch can be a liability. Consider
a circuit where the output voltage at one channel may be
changed on the fly by changing the VID code or switching
in different feedback resistors. A downward adjustment of
greater than 15% will fire the fault latch, disabling both
sides of the LTC1703 until the power is recycled. In circuits
such as this, the fault latch can be disabled by grounding
the FAULT pin. The internal latch will still be set the first
time the output exceeds +15%, but the 10µA current
source pull-up will not be able to pull FAULT high, and the
LTC1703 will ignore the latch and continue normal opera-
tion. The MAX comparator will act as usual, turning on QB
until output is within range and then allowing the loop to
resume normal operation. FAULT can also be pulled down
with external open-collector logic to restart a fault-latched
LTC1703 as an alternative to recycling the power. Note
that this will not reset the internal latch; if the external pull-
down is released, the LTC1703 will reenter FAULT mode.
To reset the latch, pull both RUN/SS pins low simulta-
neously or cycle the power.
VID Considerations
Some applications change the VID codes at channel 1 on
the fly. This is possible with the LTC1703, but care must be
taken to avoid tripping the overvoltage fault circuit. Step-
ping the voltage upwards abruptly is safe, but stepping
down quickly by more than 15% can leave the system in a
state where the output voltage is still at the old higher level,
but the feedback node is set to expect a new, substantially
lower voltage. If this condition persists for more than
25µs, the overvoltage fault circuitry will fire and latch off
the LTC1703.
The simplest solution is to disable the fault circuit by
grounding the FAULT pin. Systems that must keep the fault
circuit active should ensure that the output voltage is never
programmed to step down by more than 15% in any single
step. A safe strategy is to step the output down by 10% or
less at a time and wait for the output to settle to the new
value before taking subsequent steps. Regardless of the
state of the FAULT pin, the load is always protected against
overvoltage faults by the +5% MAX comparator.
EXTERNAL COMPONENT SELECTION
POWER MOSFETs
Getting peak efficiency out of the LTC1703 depends strongly
on the external MOSFETs used. The LTC1703 requires at
least two external MOSFETs per sidemore if one or
more of the MOSFETs are paralleled to lower on-resis-
tance. To work efficiently, these MOSFETs must exhibit
low R
DS(ON)
at 5V V
GS
(3.3V V
GS
if the PV
CC
input supply
is 3.3V) to minimize resistive power loss while they are
conducting current. They must also have low gate charge
to minimize transition losses during switching. On the
other hand, voltage breakdown requirements in a typical
LTC1703 circuit are pretty tame: the 7V maximum input
voltage limits the V
DS
and V
GS
the MOSFETs can see to
safe levels for most devices.
Low R
DS(ON)
R
DS(ON)
calculations are pretty straightforward. R
DS(ON)
is
the resistance from the drain to the source of the MOSFET
when the gate is fully on. Many MOSFETs have R
DS(ON)
specified at 4.5V gate drive—this is the right number to
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LTC1703
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use in LTC1703 circuits running from a 5V supply. As
current flows through this resistance while the MOSFET is
on, it generates I
2
R watts of heat, where I is the current
flowing (usually equal to the output current) and R is the
MOSFET R
DS(ON)
. This heat is only generated when the
MOSFET is on. When it is off, the current is zero and the
power lost is also zero (and the other MOSFET is busy
losing power).
This lost power does two things: it subtracts from the
power available at the output, costing efficiency, and it
makes the MOSFET hotter—both bad things. The effect is
worst at maximum load when the current in the MOSFETs
and thus the power lost are at a maximum. Lowering
R
DS(ON)
improves heavy load efficiency at the expense of
additional gate charge (usually) and more cost (usually).
Proper choice of MOSFET R
DS(ON)
becomes a trade-off
between tolerable efficiency loss, power dissipation and
cost. Note that while the lost power has a significant effect
on system efficiency, it only adds up to a watt or two in a
typical LTC1703 circuit, allowing the use of small, surface
mount MOSFETs without heat sinks.
Gate Charge
Gate charge is amount of charge (essentially, the number
of electrons) that the LTC1703 needs to put into the gate
of an external MOSFET to turn it on. The easiest way to
visualize gate charge is to think of it as a capacitance from
the gate pin of the MOSFET to SW (for QT) or to PGND (for
QB). This capacitance is composed of MOSFET channel
charge, actual parasitic drain-source capacitance and
Miller-multiplied gate-drain capacitance, but can be
approximated as a single capacitance from gate to source.
Regardless of where the charge is going, the fact remains
that it all has to come out of V
CC
to turn the MOSFET gate
on, and when the MOSFET is turned back off, that charge
all ends up at ground. In the meanwhile, it travels through
the LTC1703’s gate drivers, heating them up. More power
lost!
In this case, the power is lost in little bite-sized chunks, one
chunk per switch per cycle, with the size of the chunk set
by the gate charge of the MOSFET. Every time the MOSFET
switches, another chunk is lost. Clearly, the faster the
clock runs, the more important gate charge becomes as a
loss term. Old-fashioned switchers that ran at 20kHz could
pretty much ignore gate charge as a loss term; in the
550kHz LTC1703, gate charge loss can be a significant
efficiency penalty. Gate charge loss can be the dominant
loss term at medium load currents, especially with large
MOSFETs. Gate charge loss is also the primary cause of
power dissipation in the LTC1703 itself.
TG Charge Pump
There’s another nuance of MOSFET drive that the LTC1703
needs to get around. The LTC1703 is designed to use
N-channel MOSFETs for both QT and QB, primarily
because N-channel MOSFETs generally cost less and have
lower R
DS(ON)
than similar P-channel MOSFETs. Turning
QB on is no big deal since the source of QB is attached to
PGND; the LTC1703 just switches the BG pin between
PGND and V
CC
. Driving QT is another matter. The source
of QT is connected to SW which rises to V
CC
when QT is
on. To keep QT on, the LTC1703 must get TG one MOSFET
V
GS(ON)
above V
CC
. It does this by utilizing a floating driver
with the negative lead of the driver attached to SW (the
source of QT) and the V
CC
lead of the driver coming out
separately at BOOST. An external 1µF capacitor (C
CP
)
connected between SW and BOOST (Figure 2) supplies
power to BOOST when SW is high, and recharges itself
through D
CP
when SW is low. This simple charge pump
keeps the TG driver alive even as it swings well above V
CC
.
The value of the bootstrap capacitor C
CP
needs to be at
least 100 times that of the total input capacitance of the
topside MOSFET(s). For very large external MOSFETs (or
multiple MOSFETs in parallel), C
CP
may need to be
increased beyond the 1µF value.
INPUT SUPPLY
The BiCMOS process that allows the LTC1703 to include
large MOSFET drivers on-chip also limits the maximum
input voltage to 7V. This limits the practical maximum
input supply to a loosely regulated 5V or 6V rail. The
LTC1703 will operate properly with input supplies down to
about 3V, so a typical 3.3V supply can also be used if the
external MOSFETs are chosen appropriately (see the Power
MOSFETs section).
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LTC1703
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The two sides of the LTC1703 run off a single master clock
and are wired 180° out of phase with each other to
significantly reduce the total capacitance/ESR needed at
the input. Assuming 100mV of ripple and 10A output
current, we needed an ESR of 0.01 and 4.7A ripple
current capability for one side. Now, assume both sides
are running simultaneously with identical loading. If the
two sides switched in phase, all the loading conditions
would double and we’d need enough capacitance for
9.4A
RMS
and 0.005 ESR. With the two sides out of
phase, the input current is 4.8A
RMS
—barely larger than
the single case (Figure 7)! The peak current deltas are still
only 10A, requiring the same 0.01 ESR rating. As long as
the capacitor we chose for the single side application can
support the slightly higher 4.8A
RMS
current, we can add
the second channel without changing the input capacitor
at all. As a general rule, an input bypass capacitor capable
of supporting the larger output current channel can sup-
port both channels running simultaneously (see the
2-Phase Operation section for more information). Details
on how to calculate the maximum RMS input current can
be found in Application Note 77.
Tantalum capacitors are a popular choice as input capaci-
tors for LTC1703 applications, but they deserve a special
caution here. Generic tantalum capacitors have a destruc-
tive failure mechanism when they are subjected to large
RMS currents (like those seen at the input of a LTC1703).
Figure 7. Current Waveforms
At the same time, the input supply needs to supply several
amps of current without excessive voltage drop. The input
supply must have regulation adequate to prevent sudden
load changes from causing the LTC1703 input voltage to
dip. In most typical applications where the LTC1703 is
generating a secondary low voltage logic supply, all of
these input conditions are met by the main system logic
supply when fortified with an input bypass capacitor.
INPUT BYPASS CAPACITOR
A typical LTC1703 circuit running from a 5V logic supply
might provide 1.6V at 10A at one of its outputs. 5V to 1.6V
implies a duty cycle of 32%, which means QT is on 32%
of each switching cycle. During QT’s on-time, the current
drawn from the input equals the load current and during
the rest of the cycle, the current drawn from the input is
near zero. This 0A to 10A, 32% duty cycle pulse train adds
up to 4.7A
RMS
at the input. At 550kHz, switching cycles
last about 1.8µsmost system logic supplies have no
hope of regulating output current with that kind of speed.
A local input bypass capacitor is required to make up the
difference and prevent the input supply from dropping
drastically when QT kicks on. This capacitor is usually
chosen for RMS ripple current capability and ESR as well
as value.
The input bypass capacitor in an LTC1703 circuit is
common to both channels. Consider our 10A example
case with the other side of the LTC1703 disabled. The input
bypass capacitor gets exercised in three ways: its ESR
must be low enough to keep the initial drop as QT turns on
within reason (100mV or so); its RMS current capability
must be adequate to withstand the 4.7A
RMS
ripple current
at the input and the capacitance must be large enough to
maintain the input voltage until the input supply can make
up the difference. Generally, a capacitor that meets the
first two parameters will have far more capacitance than is
required to keep capacitance-based droop under control.
In our example, we need 0.01 ESR to keep the input drop
under 100mV with a 10A current step and 4.7A
RMS
ripple
current capacity to avoid overheating the capacitor. These
requirements can be met with multiple low ESR tantalum
or electrolytic capacitors in parallel, or with a large mono-
lithic ceramic capacitor.
0
10A
32%
68%
0
10A
32% 18%
18%
18%32%
3.2A
0
6.8A
32%
68%
QT CURRENT, SIDE 1 ONLY
(FOR 1-PHASE, 2 SIDES:
MULTIPLY CURRENT BY 2)
CURRENT IN C
IN
, SIDE 1 ONLY
I
CIN
= 4.66A
RMS
, (1-PHASE,
2 SIDES: I
CIN
= 9.3A
RMS
)
CURRENT IN C
IN
,
BOTH SIDES EQUAL LOAD
I
CIN
= 4.8A
RMS
QT1 CURRENT
QT2 CURRENT
BOTH SIDES EQUAL LOAD
2-PHASE OPERATION
6.4A
0
3.6A
32% 18%
1703 F07
32%
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LTC1703IG#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2x 550kHz Sync 2-PhSw Reg Cntr w/ 5-B VI
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New from this manufacturer.
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