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HT36HTJ51272.fm - Rev. B 7/06 EN
10 ©2003 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
Notes: 1. PLL specifications are critical for proper operation of the DDR2 DIMM. This is a subset of
parameters for the specific PLL used. Detailed PLL information is available in JEDEC Stan-
dard JESD82.
2. Static phase offset does not include jitter.
3. Period jitter and half-period jitter specifications are separate specifications that must be
met independently of each other.
4. Design target is 60ps, unless it is not achievable.
5. VOX specified at the DRAM clock input, or the test load.
6. The output slew rate is determined from the IBIS model:
Serial Presence-Detect
Table 11: PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
Parameter Symbol
0°C ≤ T
OPR
≤ +55°C
VDD = +1.8V ±0.1V
UnitsMin Max
Stabilization time
t
L–15µs
Input clock slew rate
t
LS
I
1.0 4 V/ns
SSC modulation frequency
30 33 KHz
SSC clock input frequency deviation
0.0 –0.50 %
PLL loop bandwidth (–3dB from unity gain)
2.0 – MHz
Table 12: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition Symbol Min Max Units
Supply voltage
V
DDSPD 1.7 3.6 V
Input high voltage: Logic 1; All inputs
V
IH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs
V
IL –0.6 VDDSPD × 0.3 V
Output low voltage: I
OUT = 3mA
V
OL –0.4V
Input leakage current: V
IN = GND to VDD
ILI 0.10 3 µA
Output leakage current: V
OUT = GND to VDD
ILO 0.05 3 µA
Standby current
I
SB 1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 KHz
I
CC
R
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 KHz
I
CC
W
23mA
V
DD
GND
V
DD
CU877
R = 60
R = 60
V
CK
V
CK
2
