PDF: 09005aef822553c2/Source: 09005aef822553af Micron Technology, Inc., reserves the right to change products or specifications without notice.
HT36HTJ51272.fm - Rev. B 7/06 EN
7 ©2003 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
I
DD
Specifications
Notes: 1. a = Value calculated as one module rank in this operating condition, all other module ranks
in I
DD2P (CKE LOW) mode.
b = Value calculated reflects all module ranks in this operating condition.
Precharge power-down current: All device banks idle;
t
CK =
t
CK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2P
b
252 252 252 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
I
DD2Q
b
1,980 1,476 1,260 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
IDD2N
b
2,160 1,620 1,440 mA
Active power-down current: All device banks open;
t
CK
=
t
CK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P
b
1,440 1,080 900 mA
Slow PDN exit
MR[12] = 1
360 360 360 mA
Active standby current: All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
I
DD3N
b
2,520 1,980 1,620 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX
(IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
I
DD4W
a
3,006 2,466 2,106 mA
Operating burst read current: All device banks open; Continuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS
MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are
switching
I
DD4R
a
3,006 2,736 2,106 mA
Burst refresh current:
t
CK =
t
CK (IDD); REFRESH command at every
t
RFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are
switching
IDD5
b
9,360 9,000 7,920 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD6
b
252 252 252 mA
Operating bank interleave read current: All device banks interleaving
reads, I
OUT = 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) -1 ×
t
CK (IDD);
t
CK
=
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
I
DD7
a
5,526 5,346 4,806 mA
Table 7: DDR2 IDD Specifications and Conditions – 4GB (continued)
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb
(256 Meg x 4) component data sheet
Parameter/Condition Symbol -667 -53E -40E Units
