AD7302
–12–
REV. 0
MICROPROCESSOR INTERFACING
AD7302–ADSP-2101/ADSP-2103 Interface
Figure 29 shows an interface between the AD7302 and the
ADSP-2101/ADSP-2103. The fast interface timing associated
with the AD7302 allows easy interface to the ADSP-2101/
ADSP-2103.
ADDR
DECODE
DATA BUS
ADDRESS BUS
CS
DB0
DB7
AD7302*
A/B
DMA0
DMA14
WR
EN
DMD0
DMD15
ADSP-2101*/
ADSP-2103*
WR
DMS
A**
A+1**
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
LDAC
Figure 29. AD7302–ADSP-2101/ADSP-2103 Interface
Two addresses are decoded to select loading data to either
DAC A or DAC B. LDAC is permanently tied low in this
circuit, so the selected DAC output is updated on the rising
edge of the WR signal.
Data is loaded to the AD7302 input register using the following
ADSP-21xx instruction:
DM (DAC) = MR0
MR0 = ADSP-21xx MR0 Register.
DAC = Decoded DAC Address.
AD7302–TMS32020 Interface
Figure 30 shows an interface between the AD7302 and the
TMS32020. The address decoder is used to decode the
addresses for DAC A and DAC B. Data is loaded to the
AD7302 using the following instruction:
OUT DAC, D
DAC = Decoded DAC Address.
D = Data Memory Address.
ADDR
DECODE
DATA BUS
ADDRESS BUS
CS
DB0
DB7
AD7302*
A/B
A0
A15
STRB
EN
DMD0
DMD15
TMS32020
WR
IS
A**
A+1**
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
LDAC
R/W
Figure 30. AD7302–TMS32020 Interface
In the circuit shown the LDAC is hardwired low, thus the
selected DAC output is updated on the rising edge of WR.
Some applications may require simultaneous updating of both
DACs in the AD7302. In this case the LDAC signal can be
driven from an external timer or can be controlled by the
microprocessor. One option for simultaneous updating is to
decode the LDAC from the address bus so that a write opera-
tion at this address will simultaneously update both DAC
outputs. A simple OR gate with one input driven from the
decoded address and the second input from the WR signal will
implement this function.
AD7302–8051/8088 Interface
Figure 31 shows a serial interface between the AD7302 and the
8051/8088 processors. The address decoder is used to decode
the addresses for DAC A and DAC B.
ADDR
DECODE
ADDRESS/DATA BUS
ADDRESS BUS
DB0
DB7
AD7302*
/B
A8
A15
AD0
AD7
8051/8088
OR
A**
A+1**
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
ALE
OCTAL
LATCH
Figure 31. AD7302–8051//8088 Interface
AD7302
–13–
REV. 0
APPLICATIONS
Bipolar Operation Using the AD7302
The AD7302 has been designed for single supply operation,
but bipolar operation is achievable using the circuit shown in
Figure 32. The circuit shown has been configured to achieve an
output voltage range of –5 V < V
O
< +5 V. Rail-to-rail operation
at the amplifier output is achievable using an AD820 or OP295
as the output amplifier.
The output voltage for any input code can be calculated as
follows:
V
O
= [(1+R4/R3)
×
(R2/(R1+R2)
×
(2
×
V
REF
×
D/256)] – R4
×
V
REF
/R3
where
␣␣D is the decimal equivalent of the code loaded to the DAC
and
␣␣V
REF
is the reference voltage input.
With V
REF
= 2.5 V, R1 = R3 = 10␣ k and R2 = R4 = 20 k and
V
DD
= 5␣ V.
V
OUT
= (10 × D/256) – 5 V
AD7302
V
OUT
A
10µF
0.1µF
V
DD
= 5V
V
DD
AGND
AD780/REF192
WITH V
DD
= 5V
OR
AD589 WITH V
DD
= 3V
REF IN
GND
V
OUT
V
IN
0.1µF
EXT REF
R1
10k
R2
20k
R4
20k
R3
10k
+5V
–5V
±5V
DGND
AD820/
OP295
Figure 32. Bipolar Operation Using the AD7302
Decoding Multiple AD7302 in a System
The CS pin on the AD7302 can be used in applications to
decode a number of DACs. In this application all DACs in the
system receive the same input data, but only the CS to one of
the DACs will be active at any one time allowing access to two
channels in the system. The 74HC139 is used as a two-to-four
line decoder to address any of the DACs in the system. To
prevent timing errors from occurring, the enable input should
be brought to its inactive state while the coded address inputs are
changing state. Figure 33 shows a diagram of a typical setup for
decoding multiple AD7302 devices in a system. The built-in
power-on reset circuit on the AD7302 ensures that the outputs
of all DACs in the system power up with zero volts on their
outputs.
AD7302
D0
D8
V
OUT
A
V
OUT
B
ENABLE
74HC139
DATA BUS
DGND
CODED
ADDRESS
1A
1B
1Y0
1Y1
1Y2
1Y3
V
CC
V
DD
1
AD7302
D0
D8
V
OUT
A
V
OUT
B
AD7302
D0
D8
V
OUT
A
V
OUT
B
AD7302
D0
D8
V
OUT
A
V
OUT
B
Figure 33. Decoding Multiple AD7302 DACs in a System
AD7302 As a Digitally Programmable Window Detector
A digitally programmable upper/lower limit detector using the
two DACs in the AD7302 is shown in Figure 34. The upper
and lower limits for the test are loaded to DACs A and B, which
in turn set the limits on the CMP04. If a signal at the V
IN
input
is not within the programmed window an LED will indicate the
fail condition.
AD7302
V
DD
+5V
V
OUT
A
DGND
REFIN
V
IN
PASS/FAIL
1/2 CMP04
1/6 74HC05
FAIL PASS
1k
0.1µF
10µF
WR
CS
A/B
1k
V
OUT
B
LDAC
CLR
DV
DD
PD
AGND
D0
D7
Figure 34. Programmable Window Detector
AD7302
–14–
REV. 0
Programmable Current Source
Figure 35 shows the AD7302 used as the control element of a
programmable current source. In this circuit the full-scale
current is set to 1 mA. The output voltage from the DAC is
applied across the current setting resistor of 4.7 k in series
with the full-scale setting resistor of 470 . Transistors suitable
to place in the feedback loop of the amplifier include the BC107
or the 2N3904, which enable the current source to operate from
a min V
SOURCE
of 6 V. The operating range is determined by
the operating characteristics of the of the transistor. Suitable
amplifiers include the AD820 and the OP295 both having rail-
to-rail operation on their outputs. The current for any digital
input code can be calculated as follows:
I = 2 × V
REF
× D/(5E +3 × 256) mA
AD7302
V
OUT
A
10µF0.1µF
V
DD
= 5V
V
DD
AGND
AD780/REF192
WITH V
DD
= 5V
REF IN
GND
V
OUT
V
IN
0.1µF
EXT REF
4.7k
470
+5V
LOAD
V
SOURCE
AD820/
OP295
DGND
Figure 35. Programmable Current Source
Coarse and Fine Adjustment Using the AD7302
The DACs on the AD7302 can be paired together to form a
coarse and fine adjustment function as shown in Figure 36. In
this circuit DAC A is used to provide the coarse function while
DAC B is used to provide the fine adjustment. Varying the ratio
of R1 and R2 will vary the relative effect of the coarse and fine
tune elements in the circuit. For the resistor values shown
DAC B has a resolution of 148 µV giving a fine tune range of
approximately 2 LSBs for operation with a V
DD
of 5 V and a
reference of 2.5 V. The amplifiers shown allow a rail-to-rail
output voltage to be achieved on the output. A typical applica-
tion for such a circuit would be in a setpoint controller.
AD7302
V
OUT
A
10µF
0.1µF
V
DD
= 5V
V
DD
AGND
AD780/REF192
WITH V
DD
= 5V
OR
AD589 WITH V
DD
= 3V
REF IN
GND
V
OUT
V
IN
0.1µF
EXT REF
R2
51.2k
R4
390
R1
390
+5V
V
OUT
DGND
AD820/
OP295
V
OUT
B
R3
51.2k
Figure 36. Coarse/Fine Adjust Circuit
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7302 is mounted should be designed so the analog and
digital sections are separated and confined to certain areas of the
board. If the AD7302 is in a system where multiple devices
require an AGND to DGND connection, the connection should
be made at one point only, a star ground point that should be
established as closely as possible to the AD7302. The AD7302
should have ample supply bypassing of 10 µF in parallel with
0.1 µF on the supply located as close to the package as possible,
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. The 0.1 µF capacitor should have low
Effective Series Resistance (ESR) and Effective Series Induc-
tance (ESI), such as the common ceramic types, which provide
a low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
The power supply lines of the AD7302 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching sig-
nals like clocks should be shielded with digital ground to avoid
radiating noise to other parts of the board and should never be
run near the reference inputs. Avoid crossover of digital and
analog signals. Traces on opposite sides of the board should run
at right angles to each other. This reduces the effects of feed-
through through the board. A microstrip technique is by far the
best, but not always possible with a double-sided board. In this
technique, the component side of the board is dedicated to
ground plane while signal traces are placed on the solder side.

AD7302BRZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 2.7-5.5V Parallel Input Dual VOut 8B
Lifecycle:
New from this manufacturer.
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