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AD7302BRZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD7302
–3–
REV. 0
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter (B Version) Units Conditions/Comments
t
1
0 ns min Address to Write Setup Time
t
2
0 ns min Address Valid to Write Hold Time
t
3
0 ns min Chip Select to Write Setup Time
t
4
0 ns min Chip Select to Write Hold Time
t
5
20 ns min Write Pulse Width
t
6
15 ns min Data Setup Time
t
7
4.5 ns min Data Hold Time
t
8
20 ns min Write to LDAC Setup Time
t
9
20 ns min LDAC Pulse Width
t
10
20 ns min CLR Pulse Width
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of
(V
IL
+ V
IH
)/2. tr and tf should not exceed 1 µs on any digital input.
2
See Figure 1.
A/B
CS
WR
D7–D0
LDAC
CLR
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
t
10
t
9
Figure 1. Timing Diagram for Parallel Data Write
(V
DD
= +2.7 V to +5.5 V; GND = 0 V; Reference = Internal V
DD
/2 Reference;
all specifications T
MIN
to T
MAX
unless otherwise noted)
AD7302
–4–
REV. 0
ORDERING GUIDE
Temperature Package
Model Range Options*
AD7302BN –40°C to +105°C N-20
AD7302BR –40°C to +105°C R-20
AD7302BRU –40°C to +105°C RU-20
*N = Plastic DIP; R = Small Outline; RU =Thin Shrink Small Outline.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Reference Input Voltage to AGND . . . .–0.3 V to V
DD
+ 0.3␣ V
Digital Input Voltage to DGND . . . . . –0.3 V to V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 0.3 V
V
OUT
A, V
OUT
B to AGND . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 900 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 102°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . .+260°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 700 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature, Soldering
␣ ␣ Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
␣ ␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering
␣ ␣ Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
␣ ␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7302 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD7302
–5–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1-8 D7–D0 Parallel Data Inputs. Eight-bit data is loaded to the input register of the AD7302 under the control of CS
and WR.
9 CS Chip Select. Active low logic input.
10 WR Write Input. WR is an active low logic input used in conjunction with CS and A/B to write data to the selected
DAC register.
11 A/B DAC Select. Address pin used to select writing to either DAC A or DAC B.
12 PD Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.
13 LDAC Load DAC Logic Input. When this logic input is taken low both DAC outputs are simultaneously updated with
the contents of their DAC registers. If LDAC is permanently tied low, the DACs are updated on the rising
edge of WR.
14 CLR Asynchronous Clear Input (Active Low). When this input is taken low the DAC registers are loaded with all
zeroes and the DAC outputs are cleared to zero volts.
15 V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and should be decoupled to AGND.
16 REFIN External Reference Input. This can used as the reference for both DACs. The range on this reference input is
1 V to V
DD
/2. If REFIN is directly tied to V
DD
the internal V
DD
/2 reference is selected.
17 AGND Analog Ground reference point and return point for all analog current on the part.
18 V
OUT
B Analog output voltage from DAC B. The output amplifier can swing rail to rail on its output.
19 V
OUT
A Analog output voltage from DAC A. The output amplifier can swing rail to rail on its output.
20 DGND Digital Ground reference point and return point for all digital current on the part.
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7302
(MSB) DB7
AGND
V
OUT
B
V
OUT
A
DGND
DB6
DB5
DB4
CLR
V
DD
REFIN
DB3
DB2
DB1
(LSB) DB0
CS
WR
A/B
PD
LDAC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD7302BRZ

Mfr. #:
Buy AD7302BRZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 2.7-5.5V Parallel Input Dual VOut 8B
Lifecycle:
New from this manufacturer.
Delivery:
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