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LT8310IFE#TRPBF

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LT8310
16
8310f
For more information www.linear.com/LT8310
operaTion
D1 conducts, which imposes V
IN
/(N
P
/N
S
) – V
OUT
across
inductor L1 (
ignoring voltage drop across the diode), for
the switch on-time, D • t
SW
. When the GATE signal goes
low, the switch turns off, and the primary winding volt-
age collapses
as the primary current charges the reset
resistor C
RST
. The switch node voltage (V
SW
) resonates
past V
IN
, which takes the primary winding voltage nega-
tive. The secondary winding voltage also goes negative,
for
ward diode D1 turns off, and the inductor current
flows through the catch diode, D2, which imposes –V
OUT
(again ignoring diode drop) across inductor L1 for the
switch off-time, (1 – D) • t
SW
. The output voltage may
be calculated by considering the volt-second balance in
the inductor under steady-state conditions (Equation 5),
and then solving for V
OUT
. Equation 6 makes it clear that
forcing the duty cycle to be inversely proportional to the
input voltage
would create a constant output voltage as
desired.
V
IN
N
P
/N
S
− V
OUT
⎛
⎝
⎜
⎞
⎠
⎟
•D • T
SW
+(−V
OUT
)•(1−D)• T
SW
= 0
[5]
V
OUT
=
D• V
IN
N
P
/N
S
[6]
To keep the transformer from saturating, its core flux must
be reset periodically. The LT8310 relies on resonant reset
each cycle uses a capacitor between the switch node,
SW, and ground (see Figure 2). When the main switch
turns off at the end of the duty cycle, V
SW
ramps up to
and beyond V
IN
, which cuts off secondary-side current
and forces primary-side current to charge the switching
node. Node SW resonates for half a sine wave until the
transformer voltage and current are both zero, which
leaves V
SW
= V
IN
until the next switch activation. Note that
(1) the maximum voltage on the primary switch exceeds
the
input voltage, and may be well above it, and (2) ideally,
the flux reset completes within the switch off-time before
the next cycle begins. The LT8310 controller imposes an
absolute maximum duty cycle that provides a predictable
minimum off-time (at a given switching frequency) in
which to reset the core.
LT8310
17
8310f
For more information www.linear.com/LT8310
INTV
CC
Regulator Bypassing and Operation
The GATE and SOUT pin drivers and other chip loads
are powered from the INTV
CC
pin, which is an internally
regulated supply. The internal low dropout regulator re-
quires a
capacitor from the IN
TV
CC
pin to GND for stable
operation and to store the charge for the large GATE and
SOUT switching currents; a 4.7μF capacitor is adequate
for most applications. Choose a 16V rated low ESR, X7R
ceramic capacitor for best performance. Place the capaci
-
tor close
to the LT8310 to minimize the trace length both
to
the INTV
CC
pin and to the chip ground. In shutdown,
the INTV
CC
pin sinks 125μA (typical) until the pin voltage
falls below 4.75V.
An internal current limit on the INTV
CC
output protects
the LT8310 from excessive on-chip power dissipation.
The minimum specified current limit should be consid
-
ered when choosing the switching N-channel MOSFET
and the operating frequency. Careful selection of a lower
Q
G
MOSFET allows higher GATE switching frequencies,
which leads to smaller magnetics. SOUT switching current
must be accounted for when that pin drives a MOSFET
gate, but in typical applications where SOUT is unused or
drives an
AC-coupled pulse transformer, GATE switching
dominates
the steady-state regulator load and the SOUT
current may be ignored. The MOSFET gate drive switching
current required may be calculated using Equation 7, see
the Thermal Considerations section for further information.
I
DRIVE
= Q
G
• f
SW
[7]
The INTV
CC
voltage tracks a few hundred millivolts below
the supply voltage until the regulation loop closes when
V
IN
exceeds about 10.5V. The INTV
CC
pin has its own
undervoltage disable set to 4.75V (typical) that protects
the external MOSFET from excessive power dissipation
caused by not being fully enhanced. If the INTV
CC
pin
drops below its undervoltage threshold, the GATE pin will
be forced to GND, the SOUT pin will follow the INTV
CC
voltage, and the soft-start pin will be reset.
The regulator may be overdriven from external circuitry to
reduce switching power dissipation in the LT8310 package,
or to drive a MOSFET switch with a high threshold. The
overdriven INTV
CC
pin voltage must be less than the IC
supply to avoid back-driving the V
IN
pin. The INTV
CC
pin
applicaTions inForMaTion
has its own overvoltage threshold set to 17.4V (typical) that
disables the system to protect MOSFETs rated for V
GS(MAX)
= 20V, a common specification. As with undervoltage
shutdown, the GATE pin will be forced to GND, the SOUT
pin will follow the INTV
CC
voltage, and the soft-start pin
will be reset. A 4.7μF 25V rated low ESR, X7R capacitor
is recommended when INTV
CC
is overdriven.
Programming the System Turn-On and Turn-Off
Thresholds
The system undervoltage and overvoltage thresholds are
programmed by a resistive voltage divider from V
IN
to
UVLO and OVLO, respectively (Figure 4). The falling UVLO
threshold,1.22V (nom), accurately sets the minimum op
-
erating V
IN
(Equation 8), below which the system goes into
low power mode. A 5.7μA (typical) pull-down current that
is active when the UVLO pin is below its falling threshold
provides rising hysteresis that sets the minimum start-
up V
IN
(Equation 9). The built-in comparator hysteresis
contributes a small amount to the rising threshold as well.
V
IN(UVLO FALLING)
= 1.22V •
R3
+
R2
+
R1
R2+R1
⎛
⎝
⎜
⎞
⎠
⎟
[8]
V
IN(UVLO RISING)
= V
IN(UVLO FALLING)
+
5.7µA •R3
+ 40mV •
R3+ R2+ R1
R2+ R1
⎛
⎝
⎜
⎞
⎠
⎟
[9]
The rising OVLO threshold, 1.25V (nom), accurately sets
the maximum operating V
IN
(Equation 10), above which
the system stops switching and awaits soft-start. The
built-in comparator hysteresis provides falling hysteresis
that sets the maximum restart V
IN
(Equation 11).
Figure 4. Resistor Connections for System UVLO
and OVLO Threshold Programming
GND
LT8310
UVLO
OVLO
V
IN
V
IN
R3
R2
R1
8310 F04
LT8310
18
8310f
For more information www.linear.com/LT8310
applicaTions inForMaTion
V
IN(OVLO RISING)
= 1.25V •
R3
+
R2
+
R1
R1
⎛
⎝
⎜
⎞
⎠
⎟
[10]
V
IN(OVLO FALLING)
= V
IN(OVLO RISING)
− 33mV •
R3+ R2+ R1
R1
⎛
⎝
⎜
⎞
⎠
⎟
[11]
Selecting the resistor values best proceeds as follows:
1. Choose V
IN(UVLO FALLING)
and V
IN(OVLO RISING)
for the
system
2. Choose a rising hysteresis voltage, V
HYST(UVLO RISING)
,
and calculate R3 = V
HYST(UVLO RISING)
/5.7µA
3. Calculate the sum of R2 + R1 from Equation 8
4. Calculate R1 from Equation 10, which then determines
R2, and
5. Recheck the thresholds using actual resistor values.
Programming the Duty Cycle Loop Output Voltage Target
In all applications, the LT8310 duty mode control loop
must have
a programmed output voltage target,
V
OUT(TARG)
, that is the value the converter would produce,
without output voltage feedback, using ideal components.
For the forward converter, this is characterized by Equation
6 (here recast with the target output).
V
OUT(TARG)
=
D• V
IN
N
P
/N
S
[12]
This is accomplished by setting the scaling factor (K
D
)
of the duty cycle versus V
IN
function and choosing the
transformer turns ratio (N
P
/N
S
). In applications without
output voltage feedback, the target voltage minus any
voltage drops (e.g., diode thresholds, ohmic losses) yields
the nominal output voltage, V
OUT
. In applications using
an opto-coupler, the target is used as an upper guard rail
level to the nominal output voltage that is set by feedback,
and it is a measure of the relative duty cycle clamp margin.
First consider the transformer turns ratio in the core
schematic in Figure 5. Since duty mode control forces the
duty cycle to be inversely proportional the input voltage,
the largest duty cycle occurs at the lowest operating input
voltage. For a given target output voltage and minimum
input voltage, the LT8310’s maximum duty cycle limit,
75% (min), constrains the turns ratio per Equation 13.
N
P
N
S
<
0.75 • V
IN(MIN)
V
OUT(TARG)
[13]
After fixing the turns ratio, consider the duty cycle. In gen-
eral, the
highest operating duty cycle should be maximized
to
best utilize the MOSFET each switching period, and to
reduce the effect of switching losses each in cycle. The
Figure 5. Forward Nonsynchronous Converter Core Schematic
LT8310
GATE
+V
IN
+V
OUT
–V
OUT
–V
IN
V
IN
L1
N
P
:N
S
T1
D1
D2
C
RST
R
SENSE
C
REG
M1
••
8310 F05
V
C
NC
C
L
DFILT
INTV
CC
RDVIN
SENSE
GND
FBX
R
SET
C
FLT
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LT8310IFE#TRPBF

Mfr. #:
Buy LT8310IFE#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 100Vin For Conv Cntr
Lifecycle:
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