ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 42
ICS1894-32 REV M 021512
100M MII Media Independent Interface: Receive Latency
The table below lists the significant time periods for the 100M MII/100M Stream Interface receive latency. The time
periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• RXCLK
• RXD (that is, RXD[3:0])
The 100M MII/100M Stream Interface: Receive Latency Timing Diagram shows the timing diagram for the time
periods.
100M MII/100M Stream Interface: Receive Latency Timing Diagram
Reset: Power-On Reset
The table below lists the significant time periods for the power-on reset. The time periods consist of timings of
signals on the following pins:
• VDD
• TXCLK
The Power-On Reset Timing Diagram shows the timing diagram for the time periods.
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 First Bit of /J/ into TP_RX to /J/ on RXD 100M MII – 16 17 Bit times
RXCLK
TP_RX
†
†
Shown
unscrambled.
RXD
t1
Time
Period
Parameter Conditions Min. Typ. Max. Units
t1 VDD ≥ 2.7 V to Reset Complete – 40 45 500 ms
