ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 44
ICS1894-32 REV M 021512
Reset: Hardware Reset and Power-Down
The table below lists the significant time periods for the hardware reset and power-down reset. The time periods
consist of timings of signals on the following pins:
• REFIN
• RESETn
• TXCLK
The Hardware Reset and Power-Down Timing Diagram shows the timing diagram for the time periods.
Hardware Reset and Power-Down Timing Diagram
Time
Period
Parameter Conditions Min. Typ. Max
.
Units
t1 RESETn Active to Device Isolation and Initialization – – 60 – ns
t2 Minimum RESETn Pulse Width – 200 – ns
t3 RESETn Released to TXCLK Valid – – 35 500 ms
REFIN
RESETn
t1
t2 t3
TXCLK Valid
Power
Consumption
(AC only)
