TEF6730A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 21 February 2007 23 of 58
NXP Semiconductors
TEF6730A
Front-end for digital-IF car radio
8.2.3 Write mode: data byte PLLM
8.2.4 Write mode: data byte PLLL
8.2.5 Write mode: data byte DAA
1 DAASW antenna DAA mode in FM
0 = standard; DAA output voltage is controlled by V
tune
1 = DAA output voltage is a fixed temperature stable voltage
controlled by the DAA setting (independent of V
tune
)
0 CFSW ceramic filter switch
0 = CFSW1 pin active (low-impedance) and CFSW2 pin inactive
(high-impedance)
1 = CFSW2 pin active (low-impedance) and CFSW1 pin inactive
(high-impedance)
Table 15. CONTROL - data byte 0h bit description
…continued
Bit Symbol Description
Table 16. PLLM - data byte 1h bit allocation with default setting
7 6 5 4 3 2 1 0
CPOFF PLL14 PLL13 PLL12 PLL11 PLL10 PLL9 PLL8
00001000
Table 17. PLLM - data byte 1h bit description
Bit Symbol Description
7 CPOFF charge pump off
0 = standard operation
1 = charge pump deactivated
6 to 0 PLL[14:8] upper byte of PLL divider word
Table 18. PLLL - data byte 2h bit allocation with default setting
7 6 5 4 3 2 1 0
PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0
01111110
Table 19. PLLL - data byte 2h bit description
Bit Symbol Description
7 to 0 PLL[7:0] lower byte of PLL divider word; PLL[14:0] is the divider ratio N of the
VCO programmable divider; N = 1024 to 32767
Table 20. DAA - data byte 3h bit allocation with default setting
7 6 5 4 3 2 1 0
AGCSW DAA6 DAA5 DAA4 DAA3 DAA2 DAA1 DAA0
01000000
