DS1977
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Read Version Command [CCh]
This command allows the master to read the chip revision code of the DS1977. After issuing the command code,
the master sends two 00h-bytes to access the version register. With the next 16 time slots the master receives two
copies of the content of the version register. Additional read-time slots will read logic 1's. Only the upper 3 bits of
the version register are valid. The lower 5 bits will all read 0.
1-Wire BUS SYSTEM
The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the DS1977 is
a slave device. The bus master is typically a microcontroller or PC. For small configurations the 1-Wire
communication signals can be generated under software control using a single port pin. A second port pin is
required to control the strong pullup to supply power for the commands Copy Scratchpad with Password, Read
Memory with Password and Verify Password. Alternatively, the DS2480B 1-Wire line driver chip or serial port
adapters based on this chip (DS9097U series) are can be used. This simplifies the hardware design and frees the
microprocessor from responding in real-time.
The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence,
and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus
state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a more
detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at
the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain or tri-state
outputs. The 1-Wire port of the DS1977 is open-drain with an internal circuit equivalent to that shown in Figure 8.
A multi-drop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus has a
maximum data rate of 15.3 kbits per second. The speed can be boosted to 125 kbits per second by activating the
Overdrive mode. The value of the pullup resistor primarily depends on the network size and load conditions. For
most applications the optimal value of the pullup resistor will be approximately 2.2kΩ for standard speed and 1.5kΩ
for Overdrive speed.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be
left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs
(Overdrive speed) or more than 120µs (standard speed), one or more devices on the bus may be reset.
TRANSACTION SEQUENCE
The protocol for accessing the DS1977 through the 1-Wire port is as follows:
Initialization
ROM Function Command
Memory Function Command
Transaction/Data
Illustrations of the transaction sequence for the various memory function commands are found later in this
document.
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence
pulse lets the bus master know that the DS1977 is on the bus and is ready to operate. For more details, see the 1-
Wire Signaling section.
1-Wire ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the eight ROM function commands. All ROM
function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure 9).
