DS1977
22 of 29
devices into a smoother low-bandwidth transition. The slew rate control is specified by the parameter t
FPD
,
which has different values for standard and Overdrive speed.
2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot.
This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed.
3) There is a hysteresis at the low-to-high switching threshold V
TH
. If a negative glitch crosses V
TH
but doesn’t go
below V
TH
- V
HY
, it will not be recognized (Figure 12, Case A). The hysteresis is effective at any 1-Wire speed.
4) There is a time window specified by the rising edge hold-off time t
REH
during which glitches will be ignored,
even if they extend below V
TH
- V
HY
threshold (Figure 12, Case B, t
GL
< t
REH
). Deep voltage droops or glitches
that appear late after crossing the V
TH
threshold and extend beyond the t
REH
window cannot be filtered
out and will be taken as beginning of a new time slot (Figure 12, Case C, t
GL
≥ t
REH
).
Only devices which have the parameters t
FPD
, V
HY
and t
REH
specified in their electrical characteristics use the
improved 1-Wire front end.
Figure 12. NOISE SUPPRESSION SCHEME
CRC GENERATION
With the DS1977 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8-bit type
and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the
first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1977 to determine if the ROM data
has been received error-free. The equivalent polynomial function of this CRC is: X
8
+ X
5
+ X
4
+ 1. This 8-bit CRC is
received in the true (non-inverted) form. It is computed at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function x
16
+ x
15
+ x
2
+ 1. This CRC is used for error detection when reading the memory using the Read Memory with Password
command and for fast verification of a data transfer when writing to or reading from the scratchpad. In contrast to
the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRC-generator inside the DS1977
chip (Figure 13) will calculate a new 16-bit CRC as shown in the command flow chart of Figure 9. The bus master
compares the CRC value read from the device to the one it calculates from the data and decides whether to
continue with an operation or to reread the portion of the data with the CRC error. With the initial pass through the
Read Memory with Password flow chart, the 16-bit CRC value is the result of shifting the command byte into the
cleared CRC generator, followed by the 2 address bytes and the data bytes. The password is excluded from the
CRC calculation. Subsequent passes through the Read Memory with Password flow chart will generate a 16-bit
CRC that is the result of clearing the CRC generator and then shifting in the data bytes.
With the Write Scratchpad command the CRC is generated by first clearing the CRC generator and then shifting in
the command code, the Target Addresses TA1 and TA2 and all the data bytes. The DS1977 will transmit this CRC
only if the data bytes written to the scratchpad include scratchpad ending offset 3Fh. The data may start at any
location within the scratchpad.
With the Read Scratchpad command the CRC is generated by first clearing the CRC generator and then shifting in
the command code, the Target Addresses TA1 and TA2, the E/S byte, and the scratchpad data starting at the
target address. The DS1977 will transmit this CRC only if the reading continues through the end of the scratchpad,
regardless of the actual ending offset.
For more information on generating CRC values see Application Note 27.
