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LPC2214FBD144/01,5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
LPC2212_2214 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 14 June 2011 13 of 47
NXP Semiconductors
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers
time (no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of
full on-chip user flash. With the CRP off, full access to the chip via the JTAG and/or ISP is
restored.
6.3 On-chip static RAM
On-chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8 bit, 16 bit, and 32 bit. The LPC2212/2214 provide 16 kB of static RAM.
6.4 Memory map
The LPC2212/2214 memory maps incorporate several distinct regions, as shown in the
following figures.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.18
“System control”.
LPC2212_2214 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 14 June 2011 14 of 47
NXP Semiconductors
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers
6.5 Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and
categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt ReQuest (IRQ), and
non-vectored IRQ as defined by programmable settings. The programmable assignment
scheme means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted.
The FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ, because then
the FIQ service routine can simply start dealing with that device. But if more than one
request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC
that identifies which FIQ source(s) is (are) requesting an interrupt.
Fig 3. LPC2212/2214 memory map
AHB PERIPHERALS
APB PERIPHERALS
RESERVED ADDRESS SPACE
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP FLASH MEMORY)
RESERVED ADDRESS SPACE
16 kB ON-CHIP STATIC RAM
RESERVED ADDRESS SPACE
256 kB ON-CHIP FLASH MEMORY (LPC2214)
0xFFFF FFFF
0xF000 0000
0xEFFF FFFF
0xE000 0000
0xC000 0000
0xDFFF FFFF
0x8000 0000
0x7FFF FFFF
0x7FFF E000
0x7FFF DFFF
0x4000 4000
0x4000 3FFF
0x4000 0000
0x3FFF FFFF
0x0004 0000
0x0003 FFFF
0x0002 0000
4.0 GB
3.75 GB
3.5 GB
3.0 GB
2.0 GB
1.0 GB
128 kB ON-CHIP FLASH MEMORY (LPC2212)
0x0001 FFFF
0x0000 0000
0.0 GB
002aad183
LPC2212_2214 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 14 June 2011 15 of 47
NXP Semiconductors
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has
one interrupt line connected to the Vectored Interrupt Controller, but may have several
internal interrupt flags. Individual interrupt flags may also represent more than one
interrupt source.
Table 4. Interrupt sources
Block Flag(s) VIC channel #
WDT Watchdog Interrupt (WDINT) 0
- Reserved for software interrupts only 1
ARM Core EmbeddedICE, DbgCommRx 2
ARM Core EmbeddedICE, DbgCommTx 3
Timer 0 Match 0 to 3 (MR0, MR1, MR2, MR3) 4
Timer 1 Match 0 to 3 (MR0, MR1, MR2, MR3) 5
UART0 Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
6
UART1 Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
7
PWM0 Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8
I
2
C-bus SI (state change) 9
SPI0 SPIF, MODF 10
SPI1 and SSP
[1]
SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS 11
PLL PLL Lock (PLOCK) 12
RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13
System Control External Interrupt 0 (EINT0) 14
External Interrupt 1 (EINT1) 15
External Interrupt 2 (EINT2) 16
External Interrupt 3 (EINT3) 17
ADC ADC 18
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

LPC2214FBD144/01,5

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NXP Semiconductors
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ARM Microcontrollers - MCU ARM7 256KF/16KR/ADC
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