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LPC2214FBD144/01,5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
LPC2212_2214 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 14 June 2011 7 of 47
NXP Semiconductors
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers
P0[14]/DCD1/EINT1 92 I DCD1 — Data Carrier Detect input for UART1.
I EINT1 — External interrupt 1 input.
Note: LOW on this pin while RESET
is LOW forces on-chip bootloader to take
over control of the part after reset.
P0[15]/RI1/EINT2 99 I RI1 — Ring Indicator input for UART1.
I EINT2 — External interrupt 2 input.
P0[16]/EINT0/MAT0[2]/
CAP0[2]
100 I EINT0 — External interrupt 0 input.
O MAT0[2] — Match output for Timer 0, channel 2.
I CAP0[2] — Capture input for Timer 0, channel 2.
P0[17]/CAP1[2]/SCK1/
MAT1[2]
101 I CAP1[2] — Capture input for Timer 1, channel 2.
I/O SCK1 — Serial Clock for SPI1/SSP
[1]
. SPI clock output from master or input
to slave.
O MAT1[2] — Match output for Timer 1, channel 2.
P0[18]/CAP1[3]/MISO1/
MAT1[3]
121 I CAP1[3] — Capture input for Timer 1, channel 3.
I/O MISO1 — Master In Slave Out for SPI1/SSP
[1]
. Data input to SPI master or
data output from SPI slave.
O MAT1[3] — Match output for Timer 1, channel 3.
P0[19]/MAT1[2]/MOSI1/
CAP1[2]
122 O MAT1[2] — Match output for Timer 1, channel 2.
I/O MOSI1 — Master Out Slave In for SPI1/SSP
[1]
. Data output from SPI master
or data input to SPI slave.
I CAP1[2] — Capture input for Timer 1, channel 2.
P0[20]/MAT1[3]/SSEL1/
EINT3
123 O MAT1[3] — Match output for Timer 1, channel 3.
I SSEL1 — Slave Select for SPI1/SSP
[1]
. Selects the SPI interface as a slave.
I EINT3 — External interrupt 3 input.
P0[21]/PWM5/CAP1[3] 4 O PWM5 — Pulse Width Modulator output 5.
I CAP1[3] — Capture input for Timer 1, channel 3.
P0[22]/CAP0[0]/MAT0[0] 5 I CAP0[0] — Capture input for Timer 0, channel 0.
O MAT0[0] — Match output for Timer 0, channel 0.
P0[23] 6 I/O General purpose bidirectional digital port only.
P0[24] 8 I/O General purpose bidirectional digital port only.
P0[25] 21 I/O General purpose bidirectional digital port only.
P0[27]/AIN0/CAP0[1]/
MAT0[1]
23 I AIN0 — ADC, input 0. This analog input is always connected to its pin.
I CAP0[1] — Capture input for Timer 0, channel 1.
O MAT0[1] — Match output for Timer 0, channel 1.
P0[28]/AIN1/CAP0[2]/
MAT0[2]
25 I AIN1 — ADC, input 1. This analog input is always connected to its pin.
I CAP0[2] — Capture input for Timer 0, channel 2.
O MAT0[2] — Match output for Timer 0, channel 2.
P0[29]/AIN2/CAP0[3]/
MAT0[3]
32 I AIN2 — ADC, input 2. This analog input is always connected to its pin.
I CAP0[3] — Capture input for Timer 0, Channel 3.
O MAT0[3] — Match output for Timer 0, channel 3.
Table 3. Pin description
…continued
Symbol Pin Type Description
LPC2212_2214 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 14 June 2011 8 of 47
NXP Semiconductors
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers
P0[30]/AIN3/EINT3/
CAP0[0]
33 I AIN3 — ADC, input 3. This analog input is always connected to its pin.
I EINT3 — External interrupt 3 input.
I CAP0[0] — Capture input for Timer 0, channel 0.
P1[0] to P1[31] I/O Port 1 is a 32-bit bidirectional I/O port with individual direction controls for
each bit. The operation of port 1 pins depends upon the pin function selected
via the Pin Connect Block.
Pins 2 through 15 of port 1 are not available.
P1[0]/CS0 91 O LOW-active Chip Select 0 signal.
(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)
P1[1]/OE 90 O LOW-active Output Enable signal.
P1[16]/TRACEPKT0 34 O Trace Packet, bit 0. Standard I/O port with internal pull-up.
P1[17]/TRACEPKT1 24 O Trace Packet, bit 1. Standard I/O port with internal pull-up.
P1[18]/TRACEPKT2 15 O Trace Packet, bit 2. Standard I/O port with internal pull-up.
P1[19]/TRACEPKT3 7 O Trace Packet, bit 3. Standard I/O port with internal pull-up.
P1[20]/TRACESYNC 102 O Trace Synchronization; standard I/O port with internal pull-up.
Note: LOW on this pin while RESET
is LOW, enables pins P1[25:16] to
operate as Trace port after reset.
P1[21]/PIPESTAT0 95 O Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P1[22]/PIPESTAT1 86 O Pipeline Status, bit 1. Standard I/O port with internal pull-up.
P1[23]/PIPESTAT2 82 O Pipeline Status, bit 2. Standard I/O port with internal pull-up.
P1[24]/TRACECLK 70 O Trace Clock. Standard I/O port with internal pull-up.
P1[25]/EXTIN0 60 I External Trigger Input. Standard I/O with internal pull-up.
P1[26]/RTCK 52 I/O Returned Test Clock output. Extra signal added to the JTAG port. Assists
debugger synchronization when processor frequency varies. Bidirectional pin
with internal pull-up.
Note: LOW on this pin while RESET
is LOW, enables pins P1[31:26] to
operate as Debug port after reset.
P1[27]/TDO 144 O Test Data out for JTAG interface.
P1[28]/TDI 140 I Test Data in for JTAG interface.
P1[29]/TCK 126 I Test Clock for JTAG interface. This clock must be slower than
1
⁄
6
of the CPU
clock (CCLK) for the JTAG interface to operate.
P1[30]/TMS 113 I Test Mode Select for JTAG interface.
P1[31]/TRST
43 I Test Reset for JTAG interface.
P2[0] to P2[31] I/O Port 2 is a 32-bit bidirectional I/O port with individual direction controls for
each bit. The operation of port 2 pins depends upon the pin function selected
via the Pin Connect Block.
P2[0]/D0 98 I/O External memory data line 0.
P2[1]/D1 105 I/O External memory data line 1.
P2[2]/D2 106 I/O External memory data line 2.
P2[3]/D3 108 I/O External memory data line 3.
P2[4]/D4 109 I/O External memory data line 4.
P2[5]/D5 114 I/O External memory data line 5.
P2[6]/D6 115 I/O External memory data line 6.
Table 3. Pin description
…continued
Symbol Pin Type Description
LPC2212_2214 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 14 June 2011 9 of 47
NXP Semiconductors
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers
P2[7]/D7 116 I/O External memory data line 7.
P2[8]/D8 117 I/O External memory data line 8.
P2[9]/D9 118 I/O External memory data line 9.
P2[10]/D10 120 I/O External memory data line 10.
P2[11]/D11 124 I/O External memory data line 11.
P2[12]/D12 125 I/O External memory data line 12.
P2[13]/D13 127 I/O External memory data line 13.
P2[14]/D14 129 I/O External memory data line 14.
P2[15]/D15 130 I/O External memory data line 15.
P2[16]/D16 131 I/O External memory data line 16.
P2[17]/D17 132 I/O External memory data line 17.
P2[18]/D18 133 I/O External memory data line 18.
P2[19]/D19 134 I/O External memory data line 19.
P2[20]/D20 136 I/O External memory data line 20.
P2[21]/D21 137 I/O External memory data line 21.
P2[22]/D22 1 I/O External memory data line 22.
P2[23]/D23 10 I/O External memory data line 23.
P2[24]/D24 11 I/O External memory data line 24.
P2[25]/D25 12 I/O External memory data line 25.
P2[26]/D26/BOOT0 13 I/O D26 — External memory data line 26.
I BOOT0 — While RESET
is LOW, together with BOOT1 controls booting and
internal operation. Internal pull-up ensures HIGH state if pin is left
unconnected.
P2[27]/D27/BOOT1 16 I/O D27 — External memory data line 27.
I BOOT1 — While RESET
is LOW, together with BOOT0 controls booting and
internal operation. Internal pull-up ensures HIGH state if pin is left
unconnected.
BOOT1:0 = 00 selects 8-bit memory on CS0 for boot.
BOOT1:0 = 01 selects 16-bit memory on CS0 for boot.
BOOT1:0 = 10 selects 32-bit memory on CS0 for boot.
BOOT1:0 = 11 selects internal flash memory.
P2[28]/D28 17 I/O External memory data line 28.
P2[29]/D29 18 I/O External memory data line 29.
P2[30]/D30/AIN4 19 I/O D30 — External memory data line 30.
I AIN4 — ADC, input 4. This analog input is always connected to its pin.
P2[31]/D31/AIN5 20 I/O D31 — External memory data line 31.
I AIN5 — ADC, input 5. This analog input is always connected to its pin.
P3[0] to P3[31] I/O Port 3 is a 32-bit bidirectional I/O port with individual direction controls for
each bit. The operation of port 3 pins depends upon the pin function selected
via the Pin Connect Block.
P3[0]/A0 89 O External memory address line 0.
P3[1]/A1 88 O External memory address line 1.
P3[2]/A2 87 O External memory address line 2.
Table 3. Pin description
…continued
Symbol Pin Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

LPC2214FBD144/01,5

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Buy LPC2214FBD144/01,5
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 256KF/16KR/ADC
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