DATASHEET
5P49V5933 MARCH 10, 2017 1 ©2017 Integrated Device Technology, Inc.
Programmable Clock Generator 5P49V5933
Description
The 5P49V5933 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock
®
5).
5P49V5933 by default uses an integrated 25MHz crystal as
input reference. It also has a redundant external clock input.
A glitchless manual switchover functions allows selection of
either one as mentioned above as input reference during
normal operation
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I
2
C
addresses to allow multiple devices to be used in a system.
Pin Assignment
Features
• Generates up to two independent output frequencies
• High performance, low phase noise PLL, < 0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
• Two fractional output dividers (FODs)
• Independent Spread Spectrum capability on each output
pair
• Two banks of internal non-volatile in-system programmable
or factory programmable OTP memory
• I
2
C serial programming interface
• One reference LVCMOS output clock
• Two universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
• I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
• Input frequency ranges:
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
• Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
• Redundant clock inputs with manual switchover
• Programmable loop bandwidth
• Programmable output to output skew
• Programmable slew rate control
• Individual output enable/disable
• Power-down mode
• 1.8V, 2.5V or 3.3V core V
DDD
, V
DDA
• Available in 24-pin VFQFPN 4mm x 4mm package
• -40° to +85°C industrial temperature operation
1
7
24-pin VFQFPN
19
13
NC
NC
V
DDA
CLKIN
NC
NC
CLKINB
CLKSEL
NC
NC
V
DDA
V
DDA
SD/OE
SEL1/SDA
SEL0/SCL
V
DDO
2
OUT2
OUT2B
OUT1B
OUT1
V
DDO
1
V
DDD
V
DDO
0
OUT0_SEL_I2CB
EPAD
2
3
4
5
6
8
9
10 11
12
14
15
16
17
18
2021222324
