5P49V5933B000LTGI Datasheet 5P49V5933B000LTGI | P4-P6

PROGRAMMABLE CLOCK GENERATOR 4 MARCH 10, 2017

5P49V5933 DATASHEET

PLL Features and Descriptions

Spread Spectrum

To help reduce electromagnetic interference (EMI), the

5P49V5933 supports spread spectrum modulation. The

output clock frequencies can be modulated to spread energy

across a broader range of frequencies, lowering system EMI.

The 5P49V5933 implements spread spectrum using the

Fractional-N output divide, to achieve controllable modulation

rate and spreading magnitude. The Spread spectrum can be

applied to any output clock, any clock frequency, and any

spread amount from ±0.25% to ±2.5% center spread and

-0.5% to -5% down spread.

Table 2: Loop Filter

PLL loop bandwidth range depends on the input reference

frequency (Fref) and can be set between the loop bandwidth

range as shown in the table below.

Table 3: Configuration Table

This table shows the SEL1, SEL0 settings to select the

configuration stored in OTP. Four configurations can be stored

in OTP. These can be factory programmed or user

programmed.

At power up time, the SEL0 and SEL1 pins must be tied to

either the VDDD/VDDA power supply so that they ramp with

that supply or are tied low (this is the same as floating the

pins). This will cause the register configuration to be loaded

that is selected according to Table 3 above. Providing that

OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after

the first 10ms of operation the levels of the SELx pins can be

changed, either to low or to the same level as VDDD/VDDA.

The SELx pins must be driven with a digital signal of < 300ns

Rise/Fall time and only a single pin can be changed at a time.

After a pin level change, the device must not be interrupted for

at least 1ms so that the new values have time to load and take

effect.

If OUT0_SEL_I2CB was 0 at POR, alternate configurations

can only be loaded via the I2C interface.

Table 4: Input Clock Select

Input clock select. Selects the active input reference source in

manual switchover mode.

0 = Integrated XTAL (default)

1 = CLKIN, CLKINB

CLKSEL Polarity can be changed by I

C programming as

shown in the table below.

PRIMSRC is bit 1 of Register 0x13.

Reference Clock Input Pins and

Selection

The 5P49V5933 by default uses an integrated 25MHz crystal

as input reference. It also has a redundant external clock

input. A glitchless manual switchover functions allows

selection of either one as mentioned above as input reference

during normal operation.

Either clock input can be set as the primary clock. The primary

clock designation is to establish which is the main reference

clock to the PLL. The non-primary clock is designated as the

secondary clock in case the primary clock goes absent and a

backup is needed. The PRIMSRC bit determines which clock

input will be selected as primary clock. When PRIMSRC bit is

“0”, integrated crystal is selected as the primary clock, and

when “1”, (CLKIN, CLKINB) as the primary clock.

The two reference inputs can be manually selected using the

CLKSEL pin. The SM bits must be set to “0x” for manual

switchover which is detailed in Manual Switchover Mode

section.

Manual Switchover Mode

When SM[1:0] is “0x”, the redundant inputs are in manual

switchover mode. In this mode, CLKSEL pin is used to switch

between the primary and secondary clock sources. The

primary and secondary clock source setting is determined by

the PRIMSRC bit. During the switchover, no glitches will occur

at the output of the device, although there may be frequency

and phase drift, depending on the exact phase and frequency

relationship between the primary and secondary clocks.

Input Reference

Frequency–Fref

(MHz)

Loop

Bandwidth Min

(kHz)

Loop

Bandwidth Max

(kHz)

1 40 126

350 300 1000

OUT0_SEL_I2CB

@ POR

SEL1 SEL0 I

Access

REG0:7 Config

100No00

101No01

110No02

111No03

0 X X Yes 1 I2C

defaults

0XXYes00

PRIMSRC CLKSEL Source

0 0 Integrated XTAL

0 1 CLKIN, CLKINB

1 0 CLKIN, CLKINB

1 1 Integrated XTAL

MARCH 10, 2017 5 PROGRAMMABLE CLOCK GENERATOR

5P49V5933 DATASHEET

OTP Interface

The 5P49V5933 can also store its configuration in an internal

OTP. The contents of the device's internal programming

registers can be saved to the OTP by setting burn_start

(W114[3]) to high and can be loaded back to the internal

programming registers by setting usr_rd_start(W114[0]) to

high.

To initiate a save or restore using I

C, only two bytes are

transferred. The Device Address is issued with the read/write

bit set to “0”, followed by the appropriate command code. The

save or restore instruction executes after the STOP condition

is issued by the Master, during which time the 5P49V5933 will

not generate Acknowledge bits. The 5P49V5933 will

acknowledge the instructions after it has completed execution

of them. During that time, the I

C bus should be interpreted as

busy by all other users of the bus.

On power-up of the 5P49V5933, an automatic restore is

performed to load the OTP contents into the internal

programming registers. The 5P49V5933 will be ready to

accept a programming instruction once it acknowledges its

7-bit I

C address.

Availability of Primary and Secondary I

C addresses to allow

programming for multiple devices in a system. The I

C slave

address can be changed from the default 0xD4 to 0xD0 by

programming the I2C_ADDR bit D0. VersaClock 5

Programming Guide provides detailed I

C programming

guidelines and register map.

SD/OE Pin Function

The polarity of the SD/OE signal pin can be programmed to be

either active HIGH or LOW with the SP bit (W16[1]). When SP

is “0” (default), the pin becomes active LOW and when SP is

“1”, the pin becomes active HIGH. The SD/OE pin can be

configured as either to shutdown the PLL or to enable/disable

the outputs. The SH bit controls the configuration of the

SD/OE pin The SH bit needs to be high for SD/OE pin to be

configured as SD

When configured as SD, device is shut down, differential

outputs are driven High/low, and the single-ended LVCMOS

outputs are driven low. When configured as OE, and outputs

are disabled, the outputs are driven high/low.

Table 5: SD/OE Pin Function Truth Table

Output Alignment

Each output divider block has a synchronizing POR pulse to

provide startup alignment between outputs. This allows

alignment of outputs for low skew performance. The phase

alignment works both for integer output divider values and for

fractional output divider values.

Besides the POR at power up, the same synchronization reset

is also triggered when switching between configurations with

the SEL0/1 pins. This ensures that the outputs remain aligned

in every configuration. This reset causes the outputs to

suspend for a few hundred microseconds so the switchover is

not glitch-less. The reset can be disabled for applications

where glitch-less switch over is required and alignment is not

critical.

When using I

C to reprogram an output divider during

operation, alignment can be lost. Alignment can be restored

by manually triggering the reset through I

When alignment is required for outputs with different

frequencies, the outputs are actually aligned on the falling

edges of each output by default. Rising edge alignment can

also be achieved by utilizing the programmable skew feature

to delay the faster clock by 180 degrees. The programmable

skew feature also allows for fine tuning of the alignment.

For details of register programming, please see VersaClock 5

Family Register Descriptions and Programming Guide for

details.

SD/OE Input

OEn

OSn

Global Shutdown

OUTn

SH bit SP bit OSn bit OEn bit SD/OE OUTn

0 0 0 x x Tri-state

0 0 1 0 x Output active

0 0 1 1 0 Output active

0 0 1 1 1 Output driven High Low

0 1 0 x x Tri-state

0 1 1 0 x Output active

0 1 1 1 0 Output driven High Low

0 1 1 1 1 Output active

1 0 0 x 0 Tri-state

1 0 1 0 0 Output active

1 0 1 1 0 Output active

1 1 0 x 0 Tri-state

1 1 1 0 0 Output active

1 1 1 1 0 Output driven High Low

1x x x 1

Output driven High Low

Note 1 : Global Shutdown

Note 2 : Tri-state regardless of OEn bits

PROGRAMMABLE CLOCK GENERATOR 6 MARCH 10, 2017

5P49V5933 DATASHEET

Output Divides

Each of the four output divides are comprised of a 12-bit

integer counter, and a 24-bit fractional counter. The output

divide can operate in integer divide only mode for improved

performance, or utilize the fractional counters to generate any

frequency with a synthesis accuracy better than 50ppb.

The Output Divide also has the capability to apply a spread

modulation to the output frequency. Independent of output

frequency, a triangle wave modulation between 30 and 63kHz

may be generated.

Output Skew

For outputs that share a common output divide value, there

will be the ability to skew outputs by quadrature values to

minimize interaction on the PCB. The skew on each output

can be adjusted from 0 to 360 degrees. Skew is adjusted in

units equal to 1/32 of the VCO period. So, for 100 MHz output

and a 2800 MHz VCO, you can select how many 11.161ps

units you want added to your skew (resulting in units of 0.402

degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so

on. The granularity of the skew adjustment is always

dependent on the VCO period and the output period.

Output Drivers

The OUT1 to OUT4 clock outputs are provided with

type in the appropriate register, any of these outputs can

support LVCMOS, LVPECL, HCSL or LVDS logic levels

The operating voltage ranges of each output is determined by

its independent output power pin (V

DDO

) and thus each can

have different output voltage levels. Output voltage levels of

2.5V or 3.3V are supported for differential HCSL, LVPECL

operation, and 1. 8V, 2.5V, or 3.3V are supported for LVCMOS

and differential LVDS operation.

Each output may be enabled or disabled by register bits.

When disabled an output will be in a logic 0 state as

determined by the programming bit table shown on page 6.

LVCMOS Operation

When a given output is configured to provide LVCMOS levels,

then both the OUTx and OUTxB outputs will toggle at the

selected output frequency. All the previously described

configuration and control apply equally to both outputs.

Frequency, phase alignment, voltage levels and enable /

disable status apply to both the OUTx and OUTxB pins. The

OUTx and OUTxB outputs can be selected to be

phase-aligned with each other or inverted relative to one

another by register programming bits. Selection of

phase-alignment may have negative effects on the phase

noise performance of any part of the device due to increased

simultaneous switching noise within the device.

Device Hardware Configuration

The 5P49V5933 supports an internal One-Time

Programmable (OTP) memory that can be pre-programmed

at the factory with up to 4 complete device configuration.

These configurations can be over-written using the serial

interface once reset is complete. Any configuration written via

the programming interface needs to be re-written after any

power cycle or reset. Please contact IDT if a specific

factory-programmed configuration is desired.

Device Start-up & Reset Behavior

The 5P49V5933 has an internal power-up reset (POR) circuit.

The POR circuit will remain active for a maximum of 10ms

after device power-up.

Upon internal POR circuit expiring, the device will exit reset

and begin self-configuration.

The device will load internal registers according to Ta bl e 3 .

Once the full configuration has been loaded, the device will

respond to accesses on the serial port and will attempt to lock

the PLL to the selected source and begin operation.

Power Up Ramp Sequence

VDDA and VDDD must ramp up together. VDDO0~2 must

ramp up before, or concurrently with, VDDA and VDDD. All

power supply pins must be connected to a power rail even if

the output is unused. All power supplies must ramp in a linear

fashion and ramp monotonically.

VDDO0~2

VDDA

VDDD

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5P49V5933B000LTGI

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